CC2530ZDK Datasheet, PDF (21/34 Pages) Texas Instruments – A True System-on-Chip Solution for 2.4-GHz IEEE 802.15.4 and ZigBee Applications

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CC2530F32, CC2530F64
CC2530F128, CC2530F256
SWRS081B – APRIL 2009 – REVISED FEBRUARY 2011
A versatile five-channel DMA controller is available in the system, accesses memory using the XDATA memory
space, and thus has access to all physical memories. Each channel (trigger, priority, transfer mode, addressing
mode, source and destination pointers, and transfer count) is configured with DMA descriptors anywhere in
memory. Many of the hardware peripherals (AES core, flash controller, USARTs, timers, ADC interface) achieve
highly efficient operation by using the DMA controller for data transfers between SFR or XREG addresses and
flash/SRAM.
Timer 1 is a 16-bit timer with timer/counter/PWM functionality. It has a programmable prescaler, a 16-bit period
value, and five individually programmable counter/capture channels, each with a 16-bit compare value. Each of
the counter/capture channels can be used as a PWM output or to capture the timing of edges on input signals. It
can also be configured in IR Generation Mode where it counts Timer 3 periods and the output is ANDed with
the output of Timer 3 to generate modulated consumer IR signals with minimal CPU interaction.
Timer 2 (the MAC Timer) is specially designed for supporting an IEEE 802.15.4 MAC or other time-slotted
protocol in software. The timer has a configurable timer period and a 24-bit overflow counter that can be used to
keep track of the number of periods that have transpired. A 40-bit capture register is also used to record the
exact time at which a start-of-frame delimiter is received/transmitted or the exact time at which transmission
ends, as well as two 16-bit output compare registers and two 24-bit overflow compare registers that can send
various command strobes (start RX, start TX, etc.) at specific times to the radio modules.
Timer 3 and Timer 4 are 8-bit timers with timer/counter/PWM functionality. They have a programmable
prescaler, an 8-bit period value, and one programmable counter channel with an 8-bit compare value. Each of
the counter channels can be used as a PWM output.
The sleep timer is an ultralow-power timer that counts 32-kHz crystal oscillator or 32-kHz RC oscillator periods.
The sleep timer runs continuously in all operating modes except power mode 3 (PM3). Typical applications of
this timer are as a real-time counter or as a wake-up timer to come out of power mode 1 (PM1) or 2 (PM2).
The ADC supports 7 to 12 bits of resolution in a 30 kHz to 4 kHz bandwidth, respectively. DC and audio
conversions with up to eight input channels (Port 0) are possible. The inputs can be selected as single-ended or
differential. The reference voltage can be internal, AVDD, or a single-ended or differential external signal. The
ADC also has a temperature-sensor input channel. The ADC can automate the process of periodic sampling or
conversion over a sequence of channels.
The operational amplifier is intended to provide front-end buffering and gain for the ADC. Both inputs as well as
the output are available on pins, so the feedback network is fully customizable. A chopper-stabilized mode is
available for applications that need good accuracy with high gain.
The ultralow-power analog comparator enables applications to wake up from PM2 or PM3 based on an analog
signal. Both inputs are brought out to pins; the reference voltage must be provided externally. The comparator
output is connected to the I/O controller interrupt detector and can be treated by the MCU as a regular I/O pin
interrupt.
The random-number generator uses a 16-bit LFSR to generate pseudorandom numbers, which can be read by
the CPU or used directly by the command strobe processor. It can be seeded with random data from noise in the
radio ADC.
The AES encryption/decryption core allows the user to encrypt and decrypt data using the AES algorithm with
128-bit keys. The core is able to support the AES operations required by IEEE 802.15.4 MAC security, the
ZigBee network layer, and the application layer.
A built-in watchdog timer allows the CC2530 to reset itself in case the firmware hangs. When enabled by
software, the watchdog timer must be cleared periodically; otherwise, it resets the device when it times out. It can
alternatively be configured for use as a general 32-kHz timer.
USART 0 and USART 1 are each configurable as either a SPI master/slave or a UART. They provide double
buffering on both RX and TX and hardware flow control and are thus well suited to high-throughput full-duplex
applications. Each has its own high-precision baud-rate generator, thus leaving the ordinary timers free for other
uses.
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Product Folder Link(s): CC2530F32 CC2530F64 CC2530F128 CC2530F256