AFE7070_16 Datasheet, PDF (21/44 Pages) Texas Instruments – Dual 14-Bit 65-MSPS Digital-to-Analog Converter With Integrated Analog Quadrature Modulator

AFE7070
www.ti.com
SLOS761D – FEBRUARY 2012 – REVISED JANUARY 2013
Register name: CONFIG2; Address: 0x02
Write-to-clear register bits remain asserted once set. Each bit must be written to 0 before another 1 can
be captured.
BIT 7
unused
0
unused
0
unused
0
unused
0
unused
0
unused
0
Alarm_fifo_2away
1
BIT 0
Alarm_fifo_1away
1
Alarm_fifo_2away: When asserted, the FIFO pointers are 2 away from collision. (WRITE_TO_CLEAR)
Alarm_fifo_1away: When asserted, the FIFO pointers are 1 away from collision. (WRITE_TO_CLEAR)
Register name: CONFIG3; Address: 0x03 (INTERFACE SELECTION)
BIT 7
alarm_or_sdo_ena
0
sif_4pin
0
SLEEP
0
TXenable
1
SYNC
0
sync_sleep_txenable_sel
0
0
BIT 0
msb_out
0
alarm_or_sdo_e When asserted, the output of the ALARM_SDO pin is enabled.
na:
sif_4pin:
When asserted, the part is in 4-pin SPI mode. The data-out is output on the ALARM_SDO
pin. If this bit is not enabled, the alarm signal is output on the ALARM_SDO pin.
sleep:
When asserted, all blocks programmed to go to sleep in CONFIG4 and CONFIG6 registers
labeled pd_***_mask are powered down.
TXenable:
When 0, the data path is zeroed. When 1, the device transmits.
sync:
When written with a 1, the part is synced. To be resynced using the sif register, it must be
reset to 0 by writing a 0 then write a 1 to the sif to sync.
sync_sleep_
txenable_sel:
This is used to define the function of the SYNC_SLEEP pin. This pin can be used for multiple
functions, but only one at a time. When it is set to control any one of the functions, all other
functions are controlled by writing their respective sif register bits.
sync_sleep_txenable
_sel
Pin controls
00
All controlled by sif bit
01
TXENABLE
10
SYNC
11
SLEEP
msb_out:
When set, and alarm_sdo_out_ena is also set, the ALARM_SDO pin outputs the value of
daca bit 13.
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