AFE7070_16 Datasheet, PDF (17/44 Pages) Texas Instruments – Dual 14-Bit 65-MSPS Digital-to-Analog Converter With Integrated Analog Quadrature Modulator

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AFE7070
SLOS761D – FEBRUARY 2012 – REVISED JANUARY 2013
SDENB
SCLK
SDIO
Instruction Cycle
Data Transfer Cycle(s)
r/w N1 N0 A4 A3 A2 A1 A0 D7 D6 D5 D4 D3 D2 D1 D0
SDENB
SCLK
SDIO
t_s (SDENB)
t _SCLK
t_h (SDIO)
t_s ^(SDIO)
t_SCLKH t _SCLKL
Figure 37. Serial Interface Write Timing Diagram
Figure 38 shows the serial interface timing diagram for an AFE7070 read operation. SCLK is the serial interface
clock input to AFE7070. Serial data enable SDENB is an active-low input to the AFE7070. SDIO is serial data-in
during the instruction cycle. In the 3-pin configuration, SDIO is data-out from the AFE7070 during the data
transfer cycle(s), while ALARM_SDO is in a high-impedance state. In the 4-pin configuration, ALARM_SDO is
data-out from the AFE7070 during the data transfer cycle(s). At the end of the data transfer, ALARM_SDO
outputs low on the final falling edge of SCLK until the rising edge of SDENB, when it enters the high-impedance
state.
SDENB
SCLK
SDIO
Instruction Cycle
Data Transfer Cycle(s)
r/w N1 N0 A4 A3 A2 A1 A0 D7 D6 D5 D4 D3 D2 D1 D0 0
ALARM_SDO
D7 D6 D5 D4 D3 D2 D1 D0 0
SDENB
4 pin configuration 3 pin configuration
output
output
SCLK
SDIO
ALARM_SDO
Data n
Data n-1
td (Data)
Figure 38. Serial Interface Read Timing Diagram
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