ADS5270_13 Datasheet, PDF (21/31 Pages) Texas Instruments – 8-Channel, 12-Bit, 40MSPS Analog-to-Digital Converter

ADS5270
www.ti.com............................................................................................................................................... SBAS293F – JANUARY 2004 – REVISED JANUARY 2009
It is recommended that the isolation be maintained
onboard by using separate supplies to drive AVDD
and LVDD, as well as separate ground planes for
AVSS and LVSS.
The use of LVDS buffers reduces the injected noise
considerably, compared to CMOS buffers. The
current in the LVDS buffer is independent of the
direction of switching. Also, the low output swing as
well as the differential nature of the LVDS buffer
results in low-noise coupling.
RESET
After the supplies have stabilized, it is necessary to
give the device an active RESET pulse. This results
in all internal registers resetting to their default value
of 0 (inactive). Without a reset, it is possible that
some registers may be in their non-default state on
power-up. This may cause the device to malfunction.
When a reset is active, the device outputs ‘0’ code on
all channels. However, the LVDS output clocks are
unaffected by reset.
POWER-DOWN MODE
The ADS5270 has a power-down pin, referred to as
PD. Pulling PD high causes the device to enter the
power-down mode. In this mode, the reference and
clock circuitry, as well as all the channels, are
powered down. Device power consumption drops to
less than 100mW in this mode. In power-down mode,
the internal buffers driving REF_T and REF_B are
tri-stated and their outputs are forced to a voltage
roughly equal to half of the voltage on AVDD. Speed
of recovery from power-down mode depends on the
value of the external capacitance on the REF_T and
REF_B pins. For capacitances on REF_T and REF_B less
than 1µF, the reference voltages settle to within 1%
of their steady-state values in less than 500µs.
Individual channels can also be selectively powered
down by programming registers.
The ADS5270 also has an internal circuit that
monitors the state of stopped clocks. If ADCLK is
stopped for longer than 300ns (or if it runs at a speed
less than 3MHz), this monitoring circuit generates a
logic signal that puts the device in a partial
power-down state. As a result, the power
consumption of the device is reduced when ADCLK is
stopped. The recovery from such a partial
power-down takes approximately 100µs; this is
described in Table 2.
LAYOUT OF PCB WITH PowerPAD
THERMALLY-ENHANCED PACKAGES
The ADS5270 is housed in an 80-lead PowerPAD
thermally-enhanced package. To make optimum use
of the thermal efficiencies designed into the
PowerPAD package, the printed circuit board (PCB)
must be designed with this technology in mind.
Please refer to SLMA004 PowerPAD brief PowerPAD
Made Easy (refer to our web site at www.ti.com),
which addresses the specific considerations required
when integrating a PowerPAD package into a PCB
design. For more detailed information, including
thermal modeling and repair procedures, please see
the technical brief SLMA002, PowerPAD
Thermally-Enhanced Package (www.ti.com).
Interfacing High-Speed LVDS Outputs (SBOA104),
an application report discussing the design of a
simple deserializer that can deserialize LVDS outputs
up to 840Mbps, can also be found on the TI web site
(www.ti.com).
CONNECTING HIGH-SPEED,
MULTI-CHANNEL ADCs TO XILINX FPGAs
A separate application note (XAPP774) describing
how to connect TI's high-speed, multi-channel ADCs
with serial LVDS outputs to Xilinx FPGAs can be
downloaded directly from the Xilinx web site
(http://www.xilinx.com).
Table 2. Time Constraints Associated with Device Recovery from Power-Down and Clock Stoppage
DESCRIPTION
Recovery from power-down mode (PD = 1 to PD = 0).
Recovery from momentary clock stoppage ( < 300ns).
Recovery from extended clock stoppage ( > 300ns).
TYP
500µs
10µs
100µs
REMARKS
Capacitors on REF_T and REF_B less than 1µF.
Copyright © 2004–2009, Texas Instruments Incorporated
Product Folder Link(s): ADS5270
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