ADS5270_13 Datasheet, PDF (18/31 Pages) Texas Instruments – 8-Channel, 12-Bit, 40MSPS Analog-to-Digital Converter

ADS5270
SBAS293F – JANUARY 2004 – REVISED JANUARY 2009............................................................................................................................................... www.ti.com
Figure 16 shows a detailed RLC model of the
sample-and-hold circuit. The circuit operates in two
phases. In the sample phase, the input is sampled on
two capacitors that are nominally 4pF. The sampling
circuit consists of a low-pass RC filter at the input to
filter out noise components that might be differentially
coupled on the input pins. The next phase is the hold
phase wherein the voltage sampled on the capacitors
is transferred (using the amplifier) to a subsequent
pipeline ADC stage.
INPUT OVER-VOLTAGE RECOVERY
The differential full-scale range supported by the
ADS5270 is nominally 2.03V. The ADS5270 is
specially designed to handle an over-voltage
condition where the differential peak-to-peak voltage
can exceed up to twice the ADC full-scale range. If
the input common-mode is not considerably off from
V_CM during overload (less than 300mV around the
nominal value of 1.45V), recovery from an
over-voltage pulse input of twice the amplitude of a
full-scale pulse is expected to be within three clock
cycles when the input switches from overload to zero
signal. All of the amplifiers in the SHA and ADC are
specially designed for excellent recovery from an
overload signal.
In most applications, the ADC inputs are driven with
differential sinusoidal inputs. While the pulse-type
signal remains at peak overload conditions
throughout its HIGH state, the sinusoid signal only
attains peak overload intermittently, at its minima and
maxima. This condition is much less severe for the
ADC input and the recovery of the ADC output (to 1%
of full-scale around the expected code). This typically
happens within the second clock when the input is
driven with a sinusoid of amplitude equal to twice that
of the ADC differential full-scale range.
IN
OUT
5nH
to 9nH
IN_P
1.5pF to
2.5pF
15Ω
to 25Ω
15Ω
3.2pF
to 25Ω ^{to 4.8pF}
60Ω
to 120Ω
1Ω
IN
OUT
IN
OUT
500Ω
to 720Ω
OUT
500Ω
to 720Ω
1.5pF
to 1.9pF
15Ω
to 25Ω
IN
15Ω
3.2pF
to 25Ω ^{to 4.8pF}
15Ωto 35Ω
60Ω
to 120Ω
5nH
to 9nH
IN_N
1.5pF to
2.5pF
IN
OUT
Switches that are ON
in SAMPLE phase.
IN
OUT
1Ω
Switches that are ON
in HOLD phase.
IN
OUT
Figure 16. Overall Structure of the Sample-and-Hold Circuit
OUT_P
OUT_N
18
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