TMS320TCI6608 Datasheet, PDF (201/230 Pages) Texas Instruments – Multicore Fixed and Floating-Point Digital Signal Processor

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7.13 SPI Peripheral
TMS320TCI6608
Multicore Fixed and Floating-Point Digital Signal Processor
SPRS623C—February 2012
The serial peripheral interconnect (SPI) module provides an interface between the DSP and other SPI-compliant
devices. The primary intent of this interface is to allow for connection to a SPI ROM for boot. The SPI module on
TCI6608 is supported only in Master mode. Additional chip-level components can also be included, such as
temperature sensors or an I/O expander.
7.13.1 SPI Electrical Data/Timing
7.13.1.1 SPI Timing
Table 7-67 SPI Timing Requirements
See Figure 7-38)
No.
Master Mode Timing Diagrams — Base Timings for 3 Pin Mode
7 tsu(SOMI-SPC) Input Setup Time, SPIx_SOMI valid before receive edge of SPIx_CLk. Polarity = 0 Phase = 0
7 tsu(SOMI-SPC) Input Setup Time, SPIx_SOMI valid before receive edge of SPIx_CLk. Polarity = 0 Phase = 1
7 tsu(SOMI-SPC) Input Setup Time, SPIx_SOMI valid before receive edge of SPIx_CLk. Polarity = 1 Phase = 0
7 tsu(SOMI-SPC) Input Setup Time, SPIx_SOMI valid before receive edge of SPIx_CLk. Polarity = 1 Phase = 1
8 th(SPC-SOMI) Input Hold Time, SPIx_SOMI valid after receive edge of SPIx_CLK. Polarity = 0 Phase = 0
8 th(SPC-SOMI) Input Hold Time, SPIx_SOMI valid after receive edge of SPIx_CLK. Polarity = 0 Phase = 1
8 th(SPC-SOMI)
8 th(SPC-SOMI)
End of Table 7-67
Input Hold Time, SPIx_SOMI valid after receive edge of SPIx_CLK. Polarity = 1 Phase = 0
Input Hold Time, SPIx_SOMI valid after receive edge of SPIx_CLK. Polarity = 1 Phase = 1
Min
2
2
2
2
5
5
5
5
Max Unit
ns
ns
ns
ns
ns
ns
ns
ns
Table 7-68 SPI Switching Characteristics (Part 1 of 2)
(See Figure 7-38 and Figure 7-39)
No.
1 tc(SPC)
2 tw(SPCH)
3 tw(SPCL)
4 td(SIMO-SPC)
4 td(SIMO-SPC)
4 td(SIMO-SPC)
4 td(SIMO-SPC)
5 td(SPC-SIMO)
5 td(SPC-SIMO)
5 td(SPC-SIMO)
5 td(SPC-SIMO)
6 toh(SPC-SIMO)
6 toh(SPC-SIMO)
Parameter
Min
Master Mode Timing Diagrams — Base Timings for 3 Pin Mode
Cycle Time, SPIx_CLK, All Master Modes
3*P2 ⁽¹⁾
Pulse Width High, SPIx_CLK, All Master Modes
0.5*tc - 1
Pulse Width Low, SPIx_CLK, All Master Modes
0.5*tc - 1
Setup (Delay), initial data bit valid on SPIx_SIMO to initial edge on SPIx_CLK.
Polarity = 0, Phase = 0.
Setup (Delay), initial data bit valid on SPIx_SIMO to initial edge on SPIx_CLK.
Polarity = 0, Phase = 1.
Setup (Delay), initial data bit valid on SPIx_SIMO to initial edge on SPIx_CLK
Polarity = 1, Phase = 0
Setup (Delay), initial data bit valid on SPIx_SIMO to initial edge on SPIx_CLK
Polarity = 1, Phase = 1
Setup (Delay), subsequent data bits valid on SPIx_SIMO to initial edge on
SPIx_CLK. Polarity = 0 Phase = 0
Setup (Delay), subsequent data bits valid on SPIx_SIMO to initial edge on
SPIx_CLK Polarity = 0 Phase = 1
Setup (Delay), subsequent data bits valid on SPIx_SIMO to initial edge on
SPIx_CLK Polarity = 1 Phase = 0
Setup (Delay), subsequent data bits valid on SPIx_SIMO to initial edge on
SPIx_CLK Polarity = 1 Phase = 1
Output hold time, SPIx_SIMO valid after receive edge of SPIx_CLK except for 0.5*tc - 2
final bit. Polarity = 0 Phase = 0
Output hold time, SPIx_SIMO valid after receive edge of SPIx_CLK except for 0.5*tc - 2
final bit. Polarity = 0 Phase = 1
Max
5
5
5
5
2
2
2
2
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Copyright 2012 Texas Instruments Incorporated
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