TMS320TCI6608 Datasheet, PDF (121/230 Pages) Texas Instruments – Multicore Fixed and Floating-Point Digital Signal Processor

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7.3.2 Clock Domains
TMS320TCI6608
Multicore Fixed and Floating-Point Digital Signal Processor
SPRS623C—February 2012
Cock gating to each logic block is managed by the local power/sleep controllers (LPSCs) of each module. For
modules with a dedicated clock or multiple clocks, the LPSC communicates with the PLL controller to enable and
disable that module's clock(s) at the source. For modules that share a clock with other modules, the LPSC controls
the clock gating.
Table 7-7 shows the TMS320TCI6608 clock domains.
Table 7-7
Clock Domains
LPSC Number
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
No LPSC
End of Table 7-7
Module(s)
Shared LPSC for all peripherals other than those listed in this table
SmartReflex
DDR3 EMIF
EMIF16 and SPI
TSIP
Debug Subsystem and Tracers
Per-core TETB and System TETB
Packet Accelerator
Ethernet SGMIIs
Security Accelerator
PCIe
SRIO
HyperLink
Reserved
MSMC RAM
C66x CorePac0 and Timer 0
C66x CorePac1 and Timer 1
C66x CorePac2 and Timer 2
C66x CorePac3 and Timer 3
C66x CorePac4 and Timer 4
C66x CorePac5 and Timer 5
C66x CorePac6 and Timer 6
C66x CorePac7 and Timer 7
Bootcfg, PSC, and PLL controller
Notes
Always on
Always on
Always on
Software control
Software control
Software control
Software control
Software control
Software control
Software control
Software control
Software control
Software control
Reserved
Software control
Always on
Always on
Always on
Always on
Always on
Always on
Always on
Always on
These modules do not use LPSC
Copyright 2012 Texas Instruments Incorporated
Peripheral Information and Electrical Specifications 121