TPS544B20 Datasheet, PDF (20/75 Pages) Texas Instruments – 4.5-V to 18-V, 20-A, and 30-A SWIFT Synchronous Buck Converters with PMBus

TPS544B20, TPS544C20
SLUSB69B – MAY 2014 – REVISED JULY 2016
www.ti.com
Table 2. Required RT
Resistors (continued)
NOMINAL
FREQUENCY
(kHz)
850
1000
1% RESISTOR
VALUE (kΩ)
133
205
The TPS544B20 and TPS544C20 devices detect values that are out-of-range on the RT pin. If the device
detects that RT pin has an out-of-range resistance connected to it, the device selects a frequency setting of
either 250 kHz (if the resistance is less than 5 kΩ) or 1 MHz (if the resistance is greater than 300 kΩ). In this
case, the device also asserts the IVFREQ bit in STATUS_MFR_SPECIFIC. Once VDD is applied, the frequency
latches in memory and RT pin deactives until BP6 falls below V_BP6UV. When the device has completed the
Power-on-reset sequence, it latches the frequency in memory and deactivates the RT pin until the BP6 voltage
falls below the BP6 undervoltage threshold setting.
8.3.7 Soft-Start
To control the inrush current needed to charge the output capacitors during the start-up sequence, the
TPS544C20 and TPS544B20 devices implement a soft-start time. When the device is enabled, the feedback
reference voltage, V_REF, rises from 0 V to its final value (including output margining or VREF_TRIM value) at a
slew rate defined by the TON_RISE command. The slew rate needed to increase the reference voltage from 0 V
to 600 mV at each given rise time defines the specified rise times. During the soft-start period, the error amplifier
operates as a unity-gain buffer to force the COMP pin voltage to track the internal reference and minimize the
offset between the internal reference and the output voltage. Because D-CAP mode or D-CAP2 mode control
regulates the valley voltage, the average output voltage can exceed the final regulation voltage several millivolts
at the end of the soft-start period See Figure 23.
CNTL
V_OUT
COMP
V_REF
V_COMP
STATE Off
EA AMP
TON_DELAY
Off
TON_RISE
Buffer
Figure 23. Soft-Start
NORMAL
Integrator
8.3.8 Linear Regulators BP3 and BP6
Two on-board linear regulators provide suitable power for the internal circuitry of the devices. Externally bypass
pins BP3 and BP6 for the converter to function properly. BP3 requires a minimum of 100 nF of capacitance
connected to AGND. BP6 should be bypassed to GND with a 4.7-µF capacitor.
These devices allow the use of an internal regulator to power other circuits. Ensure that external loads placed on
the regulators do not adversely affect operation of the controller. Avoid loads with heavy transient currents that
can affect the regulator outputs. Transient voltages on these outputs can result in noisy or erratic operation.
Observe the current limits. Shorting the BP3 pin to GND can damage the BP3 regulator. The BP3 regulator input
comes from the BP6 regulator output. The BP6 regulator can supply 120 mA of current and the total current
drawn from both regulators must be less than 120 mA. This total current includes the device operating current
(I_VDD) plus the gate-drive current required to drive the power MOSFETs.
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