TPS544B20 Datasheet, PDF (17/75 Pages) Texas Instruments – 4.5-V to 18-V, 20-A, and 30-A SWIFT Synchronous Buck Converters with PMBus

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TPS544B20, TPS544C20
SLUSB69B – MAY 2014 – REVISED JULY 2016
8.3 Feature Description
8.3.1 Turn-On and Turn-Off Delay and Sequencing
The TPS544C20 and TPS544B20 devices provide many sequencing options. Using the ON_OFF_CONFIG
command, the device can be configured to start up when the input voltage is above the undervoltage lockout
(UVLO) threshold, or to additionally require a signal on the CNTL pin and/or receive an update to the
OPERATION command according to the PMBus protocol. When the gating signal as specified by
ON_OFF_CONFIG command is asserted, a programmable turn-on delay can be set with the TON_DELAY
command to delay the start of regulation. Similarly, a programmable turn-off delay can be set with the
TOFF_DELAY command to delay the stop of regulation once the gating signal is de-asserted. Delay times are
specified as an integer multiple of the soft-start time.
When the output voltage remains within the PGOOD window after the start-up period, PGOOD is released, and
rises to an externally supplied logic level. The PGOOD signal can be connected to the CNTL pin of another
device to provide additional controlled turn-on and turn-off sequencing.
Figure 20 shows control of the start-up and shutdown operations of the device, when the device is configured to
respond to a logical AND of both CNTL and the OPERATION command. The device can also be configured to
respond to only the CNTL signal, only the OPERATION command, or to convert power whenever VDD is greater
than the VIN_ON command value setting.
TON_DELAY
TON_RISE
TOFF_DELAY
VIN
OPERATION[7]
OFF
ON
CNTL
OFF
V_OUT
(1) Bit 7 of OPERATION is used to control power conversion. Other bits in this register control output voltage margining.
Figure 20. Turn-On Controlled By Both Operation and Control
8.3.2 Pre-Biased Output Start-Up
The TPS544C20 and TPS544B20 devices prevent current from discharging from the output during start-up, when
a pre-biased output condition exists. No SW pulses occur until the internal soft-start voltage rises above the error
amplifier input voltage (FB pin), if the output is pre-biased. When the soft-start voltage exceeds the error amplifier
input, and SW pulses start, the device limits synchronous rectification time after each SW pulse with a narrow
on-time. The low-side MOSFET on-time slowly increases each switching cycle until it generates 128 pulses. After
128 pulses, the synchronous rectifier runs fully complementary to the high-side MOSFET. This approach
prevents the sinking of current from a pre-biased output, and ensures the output voltage start-up and ramp-to-
regulation sequences are smooth and monotonic. These devices respond to a pre-biased output over-voltage
condition immediately upon power-up, even during soft-start, while disabled or below the PMBus programmable
undervoltage lockout on-time (UVLO_ON).
The combination of D-CAP and D-CAP2 mode control and the limited on-time of the low-side MOSFET during
the pre-bias sequence allows these devices to operate at low switching frequencies for the first 128 switching
cycles, after which the device operates using pseudo-constant frequency.
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