TMS470MF03107 Datasheet, PDF (20/67 Pages) Texas Instruments – TMS470MF04207/TMS470MF03107 16/32-Bit RISC Flash Microcontroller

TMS470MF04207
TMS470MF03107
SPNS159C – JANUARY 2012
3 Device Configurations
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3.1 Reset/Abort Sources
Resets/aborts are handled as shown in Table 3-1.
Table 3-1. Reset/Abort Sources
ERROR SOURCE
1) CPU TRANSACTIONS
Precise write error (NCNB/Strongly Ordered)
Precise read error (NCB/Device or Normal)
Imprecise write error (NCB/Device or Normal)
External imprecise error (Illegal transaction with ok
response)
Illegal instruction
SYSTEM MODE
User/Privilege
User/Privilege
User/Privilege
User/Privilege
User/Privilege
M3 Lockup
MPU access violation
User/Privilege
User/Privilege
2) SRAM
ECC single error (correctable)
ECC double error (uncorrectable)
User/Privilege
User/Privilege
3) FLASH WITH ECC
ECC single error (correctable)
ECC double error (uncorrectable)
User/Privilege
User/Privilege
8) HET
HET Memory parity error
User/Privilege
9) MIBSPI
MibSPI1 memory parity error
MibSPI2 memory parity error
User/Privilege
User/Privilege
10) MIBADC
Memory parity error
User/Privilege
11) DCAN/CAN
DCAN1 memory parity error
DCAN2 memory parity error
User/Privilege
User/Privilege
13) PLL
PLL slip error
User/Privilege
14) CLOCK MONITOR
Clock monitor interrupt
User/Privilege
19) VOLTAGE REGULATOR
Vcc out of range
n/a
20) CPU SELFTEST (LBIST)
CPU Selftest (LogicBIST) error
User/Privilege
21) ERRORS REFLECTED IN THE SYSESR REGISTER
Power-Up Reset/Vreg out of voltage⁽²⁾
n/a
ERROR RESPONSE
Precise Abort (CPU)
Precise Abort (CPU)
Imprecise Abort (CPU)
ESM
Undefined Instruction Trap
(CPU) ⁽¹⁾
ESM => NMI
Abort (CPU)
ESM
ESM => NMI
ESM
ESM => NMI
ESM
ESM
ESM
ESM
ESM
ESM
ESM
ESM
Reset
ESM
Reset
ESM HOOKUP,
GROUP.CHANNEL
n/a
n/a
n/a
2.17
n/a
2.16
n/a
1.26
2.6
1.6
2.4
1.7
1.17
1.18
1.19
1.21
1.23
1.10
1.11
n/a
1.27
n/a
(1) The undefined instruction trap is NOT detected outside of the CPU. The trap is taken only if the code reaches the execute stage of the
CPU.
(2) Both a power-on reset and Vreg out-of-range reset are indicated by the PORST bit in the SYSESR register.
20
Device Configurations
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