THS3110_14 Datasheet, PDF (20/38 Pages) Texas Instruments – LOW-NOISE, HIGH-VOLTAGE, CURRENT-FEEDBACK OPERATIONAL AMPLIFIERS

THS3110
THS3111
SLOS422E – SEPTEMBER 2003 – REVISED OCTOBER 2009........................................................................................................................................ www.ti.com
Figure 62 shows the total system output impedance
which includes the amplifier output impedance in
parallel with the feedback plus gain resistors, which
cumulate to 1870 Ω. Figure 51 shows this circuit
configuration for reference.
2000
1800
1600
1400
1200
1000
800
600
400 Gain = 2
200
R_F = 1 kΩ
V_S = ±15 V and ±5 V
0
100 k 1 M
10 M
100 M 1 G
f - Frequency - Hz
Figure 62. Power-Down Output Impedance vs
Frequency
POWER-DOWN REFERENCE PIN
OPERATION
In addition to the power-down pin, the THS3110
features a reference pin (REF) which allows the user
to control the enable or disable power-down voltage
levels applied to the PD pin. In most split-supply
applications, the reference pin is connected to
ground. In either case, the user needs to be aware of
voltage-level thresholds that apply to the power-down
pin. The tables below show examples and illustrate
the relationship between the reference voltage and
the power-down thresholds. In the table, the threshold
levels are derived by the following equations:
PD ≤ REF + 0.8 V for enable
PD ≥ REF + 2.0 V for disable
where the usable range at the REF pin is
V_S– ≤ V_REF ≤ (V_S+ – 4 V).
The recommended mode of operation is to tie the
REF pin to midrail, thus setting the enable/disable
thresholds to V_midrail + 0.8 V and V_midrail + 2 V
respectively.
As with most current feedback amplifiers, the internal
architecture places some limitations on the system
when in power-down mode. Most notably is the fact
that the amplifier actually turns ON if there is a ±0.7 V
or greater difference between the two input nodes
(V+ and V–) of the amplifier. If this difference
exceeds ±0.7 V, the output of the amplifier creates an
output voltage equal to approximately [(V+ – V–) –
0.7 V] × Gain. Also, if a voltage is applied to the
output while in power-down mode, the V– node
voltage is equal to V_O(applied) × R_G/(R_F + R_G). For low
gain configurations and a large applied voltage at the
output, the amplifier may actually turn ON due to the
aforementioned behavior.
The time delays associated with turning the device on
and off are specified as the time it takes for the
amplifier to reach either 10% or 90% of the final
output voltage. The time delays are in the order of
microseconds because the amplifier moves in and out
of the linear mode of operation in these transitions.
POWER-DOWN THRESHOLD VOLTAGE LEVELS
SUPPLY REFERENCE PIN ENABLE DISABLE
VOLTAGE (V) VOLTAGE (V) LEVEL (V) LEVEL (V)
±15, ±5
0.0
0.8
2.0
±15
2.0
2.8
4
±15
–2.0
–1.2
0
±5
1.0
1.8
3
±5
–1.0
–0.2
1
+30
15
15.8
17
+10
5.0
5.8
7
Note that if the REF pin is left unterminated, it floats
to the positive rail and falls outside of the
recommended operating range given above (V_S– ≤
V_REF ≤ V_S+ – 4 V). As a result, it no longer serves as
a reliable reference for the PD pin and the
enable/disable thresholds given above no longer
apply. If the PD pin is also left unterminated, it also
floats to the positive rail and the device is disabled. If
balanced, split supplies are used (±V_S) and the REF
and PD pins are grounded, the device is enabled.
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