OPA454_16 Datasheet, PDF (20/47 Pages) Texas Instruments – High-Voltage (100-V), High-Current (50-mA) Operational Amplifiers

OPA454
SBOS391B – DECEMBER 2007 – REVISED MARCH 2016
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9.3.5 Settling Time
The circuit in Figure 62 is used to measure the settling time response. The left half of the circuit is a standard,
false-summing junction test circuit used for settling time and open-loop gain measurement. R₁ and R₂ provide the
gain and allow for measurement without connecting a scope probe directly to the summing junction, which can
disturb proper op amp function by causing oscillation.
The right half of the circuit looks at the combination of both inverting and noninverting responses. R₅ and R₆
remove the large step response. The remaining voltage at V₂ shows the small-signal settling time that is centered
on zero. This test circuit can be used for incoming inspection, real-time measurement, or in designing
compensation circuits in system applications.
Table 1 lists the settling time measurement circuit configuration shown in Figure 62 with different gain settings.
Table 1. Settling Time Measurement Circuit Configuration Using Different Gain
Settings for Figure 62
COMPONENT
1
GAIN
5
10
R₁ (Ω)
10 k
2k
1k
R₃ (Ω)
10 k
2k
1k
R₇ (Ω)
10 k
4k
9k
R₈ (Ω)
∞
1k
1k
V_IN (V_PP)
20
16
8
Inverting Response
Measured Here, V₁
R₂
R₁
10kW
R₄
Combination of Both
R₃
10kW
Inverting and
R₇
R₈
Noninverting Responses, V₂
-IN
V_OUT
OPA454
+IN
A₁
R₅
10kW
R₆
10kW
-IN
V_OUT
OPA454
A₂
+IN
V_IN
Figure 62. Settling Time Test Measurement Circuit
20
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