OPA2680 Datasheet, PDF (20/22 Pages) Burr-Brown (TI) – Dual Wideband, Voltage Feedback OPERATIONAL AMPLIFIER With Disable

The transition edge rate (dv/dt) of the DIS control line will
influence this glitch. For the plot of Figure 15, the edge rate
was reduced until no further reduction in glitch amplitude
was observed. This approximately 1V/ns maximum slew
rate may be achieved by adding a simple RC filter into the
DIS pin from a higher speed logic line. If extremely fast
transition logic is used, a 2kΩ series resistor between the
logic gate and the DIS input pin will provide adequate
bandlimiting using just the parasitic input capacitance on the
DIS pin while still ensuring adequate logic level swing.
THERMAL ANALYSIS
Due to the high output power capability of the OPA2680,
heatsinking or forced airflow may be required under extreme
operating conditions. Maximum desired junction tempera-
ture will set the maximum allowed internal power dissipa-
tion as described below. In no case should the maximum
junction temperature be allowed to exceed 175°C.
Operating junction temperature (T_J) is given by T_A + P_D•θ_JA.
The total internal power dissipation (P_D) is the sum of
quiescent power (P_DQ) and additional power dissipated in
the output stage (P_DL) to deliver load power. Quiescent
power is simply the specified no-load supply current times
the total supply voltage across the part. P_DL will depend on
the required output signal and load but would, for a grounded
resistive load, be at a maximum when the output is fixed at
a voltage equal to 1/2 of either supply voltage (for equal
bipolar supplies). Under this condition, P_DL = V_S2/(4•R_L)
where R_L includes feedback network loading.
Note that it is the power in the output stage and not into the
load that determines internal power dissipation.
As a worst-case example, compute the maximum T_J using an
OPA2680U (SO-8 package) in the circuit of Figure 1 operat-
ing at the maximum specified ambient temperature of +85°C
and with both outputs driving a grounded 20Ω load to +2.5V.
P_D = 10V • 14.4mA + 2 [5²/(4•(20Ω || 804Ω))] = 785mW
Maximum T_J = +85°C + (0.79W • 125°C/W) = 184°C.
This absolute worst-case condition exceeds the specified
maximum junction temperature. Actual P_DL will always be
less than that considered here. Carefully consider maximum
T_J in your application.
BOARD LAYOUT GUIDELINES
Achieving optimum performance with a high frequency
amplifier like the OPA2680 requires careful attention to
board layout parasitics and external component types. Rec-
ommendations that will optimize performance include:
a) Minimize parasitic capacitance to any AC ground for all
of the signal I/O pins. Parasitic capacitance on the output
and inverting input pins can cause instability: on the non-
inverting input, it can react with the source impedance to
cause unintentional bandlimiting. To reduce unwanted ca-
pacitance, a window around the signal I/O pins should be
opened in all of the ground and power planes around those
pins. Otherwise, ground and power planes should be unbro-
ken elsewhere on the board.
b) Minimize the distance (<0.25") from the power supply
pins to high frequency 0.1µF decoupling capacitors. At the
device pins, the ground and power plane layout should not
be in close proximity to the signal I/O pins. Avoid narrow
power and ground traces to minimize inductance between
the pins and the decoupling capacitors. The power supply
connections should always be decoupled with these capaci-
tors. An optional supply decoupling capacitor (0.1µF) across
the two power supplies (for bipolar operation) will improve
2nd harmonic distortion performance. Larger (2.2µF to 6.8µF)
decoupling capacitors, effective at lower frequency, should
also be used on the main supply pins. These may be placed
somewhat farther from the device and may be shared among
several devices in the same area of the PC board.
c) Careful selection and placement of external compo-
nents will preserve the high frequency performance of
the OPA2680. Resistors should be a very low reactance
type. Surface-mount resistors work best and allow a tighter
overall layout. Metal film or carbon composition axially-
leaded resistors can also provide good high frequency per-
formance. Again, keep their leads and PC board traces as
short as possible. Never use wirewound type resistors in a
high frequency application. Since the output pin and invert-
ing input pin are the most sensitive to parasitic capacitance,
always position the feedback and series output resistor, if
any, as close as possible to the output pin. Other network
components, such as non-inverting input termination resis-
tors, should also be placed close to the package. Where
double-side component mounting is allowed, place the feed-
back resistor directly under the package on the other side of
the board between the output and inverting input pins. Even
with a low parasitic capacitance shunting the external resis-
tors, excessively high resistor values can create significant
time constants that can degrade performance. Good axial
metal film or surface-mount resistors have approximately
0.2pF in shunt with the resistor. For resistor values >1.5kΩ,
this parasitic capacitance can add a pole and/or zero below
500MHz that can effect circuit operation. Keep resistor
values as low as possible consistent with load driving con-
siderations. The 402Ω feedback used in the typical perfor-
mance specifications is a good starting point for design.
Note that a 25Ω feedback resistor, rather than a direct short,
is suggested for the unity gain follower application. This
effectively isolates the inverting input capacitance from the
output pin that would otherwise cause additional peaking in
the gain of +1 frequency response.
d) Connections to other wideband devices on the board
may be made with short direct traces or through on-board
transmission lines. For short connections, consider the trace
and the input to the next device as a lumped capacitive load.
Relatively wide traces (50 to 100mils) should be used,
preferably with ground and power planes opened up around
them. Estimate the total capacitive load and set R_S from the
plot of Recommended R_S vs Capacitive Load. Low parasitic
capacitive loads (<5pF) may not need an R_S since the
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OPA2680
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