DRV8860 Datasheet, PDF (20/31 Pages) Texas Instruments – 8 Channel Serial Interface Low-Side Driver

DRV8860
SLRS065A – SEPTEMBER 2013 – REVISED NOVEMBER 2013
www.ti.com
Output Energizing and PWM Control
The device output is defined by two stages: Energizing Phase and PWM Phase.
This special feature is designed to save energy and reduce heat for electromagnetic armature loads. It as well
can be used to adjust average output voltage for resistance load.
During the Energizing phase, the channel is turned on with 100% duty cycle for a duration set by Control register
bits C4:C1.
In PWM chopping phase, with the PWM Duty Cycle defined by Control register bits C7:C5.
The behavior of each bit in the Control Register is described in the table below:
CONTROL REGISTER SETTINGS
C8
C7
C6
C5
C4
C3
C2
C1
Value
DESCRIPTION
0
X
X
X
X
X
X
X
N/A
Outputs always in Energizing mode
1
X
X
X
0
0
0
0
0 ms
No Energizing, starts in PWM chopping
1
X
X
X
0
0
0
1
3 ms
1
X
X
X
0
0
1
0
5 ms
1
X
X
X
0
0
1
1
10 ms
1
X
X
X
0
1
0
0
15 ms
1
X
X
X
0
1
0
1
20 ms
1
X
X
X
0
1
1
0
30 ms
1
X
X
X
0
1
1
1
50 ms
1
X
X
X
1
0
0
0
80 ms
Sets the Energizing Time (100% duty cycle) before
switching to PWM Phase
1
X
X
X
1
0
0
1
110 ms
1
X
X
X
1
0
1
0
140 ms
1
X
X
X
1
0
1
1
170 ms
1
X
X
X
1
1
0
0
200 ms
1
X
X
X
1
1
0
1
230 ms
1
X
X
X
1
1
1
0
260 ms
1
X
X
X
1
1
1
1
300 ms
1
0
0
0
X
X
X
X
0%
Output is off after Energizing Phase
1
0
0
1
X
X
X
X
12.50% 12.5 kHz
1
0
1
0
X
X
X
X
25.00% 25 kHz
1
0
1
1
X
X
X
X
37.50%
1
1
0
0
X
X
X
X
50.00%
Sets PWM chopping duty cycle. DC is the
duty cycle that the low-side FET is on.
1
1
0
1
X
X
X
X
62.50% 50 kHz
1
1
1
0
X
X
X
X
75.00%
1
1
1
1
X
X
X
X
87.50%
20
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