CD54HC4051_15 Datasheet, PDF (20/45 Pages) Texas Instruments – High-Speed CMOS Logic Analog Multiplexers and Demultiplexers

CD54HC4051, CD74HC4051
CD54HCT4051, CD74HCT4051, CD54HC4052, CD74HC4052, CD54HCT4052
CD74HCT4052, CD54HC4053, CD74HC4053, CD54HCT4053, CD74HCT4053
SCHS122K – NOVEMBER 1997 – REVISED SEPTEMBER 2015
8 Detailed Description
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8.1 Overview
The CDx4HCx4051 devices are a single 8-channel multiplexer having three binary control inputs, S₀, S₁, and S₂
and an ENABLE input. The three binary signals select 1 of 8 channels to be turned on, and connect one of the 8
inputs to the output.
The CDx4HCx4052 devices are a differential 4-channel multiplexer having two binary control inputs, S₀ and S₁,
and an ENABLE input. The two binary input signals select 1 of 4 pairs of channels to be turned on and connect
the analog inputs to the outputs.
The CDx4HCx4053 devices are a triple 2-channel multiplexer having three separate digital control inputs, S₀, S₁,
and S₂ and an ENABLE input. Each control input selects one of a pair of channels that are connected in a single-
pole, double-throw configuration.
When these devices are used as demultiplexers, the CHANNEL IN/OUT terminals are the outputs and the
COMMON OUT/IN terminals are the inputs.
8.2 Functional Block Diagrams
CHANNEL IN/OUT
V_CC
16
A₇ A₆ A₅ A₄ A₃ A₂ A₁ A₀
4 2 5 1 12 15 14 13
TG
TG
S₀ 11
TG
S₁ 10
S₂ 9
LOGIC
LEVEL
CONVERSION
BINARY
TO
1 OF 8
DECODER
WITH
ENABLE
TG
A
3 COMMON
OUT/IN
TG
TG
TG
E6
TG
8
7
GND
V_EE
All inputs are protected by standard CMOS protection network.
Figure 17. CDx4HCx4051 Functional Block Diagram
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