CC2530F32_17 Datasheet, PDF (20/36 Pages) Texas Instruments – A True System-on-Chip Solution for 2.4-GHz IEEE 802.15.4 and ZigBee Applications

CC2530F32, CC2530F64
CC2530F128, CC2530F256
SWRS081B – APRIL 2009 – REVISED FEBRUARY 2011
Figure 8. CC2530 Block Diagram
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A block diagram of the CC2530 is shown in Figure 8. The modules can be roughly divided into one of three
categories: CPU- and memory-related modules; modules related to peripherals, clocks, and power management;
and radio-related modules. In the following subsections, a short description of each module that appears in
Figure 8 is given.
For more details about the modules and their usage, see the corresponding chapters in the CC253x User's
Guide (SWRU191).
CPU and Memory
The 8051 CPU core used in the CC253x device family is a single-cycle 8051-compatible core. It has three
different memory-access buses (SFR, DATA and CODE/XDATA) with single-cycle access to SFR, DATA, and
the main SRAM. It also includes a debug interface and an 18-input extended interrupt unit.
The interrupt controller services a total of 18 interrupt sources, divided into six interrupt groups, each of which
is associated with one of four interrupt priorities. Any interrupt service request is serviced also when the device is
in idle mode by going back to active mode. Some interrupts can also wake up the device from sleep mode
(power modes 1–3).
The memory arbiter is at the heart of the system, as it connects the CPU and DMA controller with the physical
memories and all peripherals through the SFR bus. The memory arbiter has four memory access points, access
of which can map to one of three physical memories: an 8-KB SRAM, flash memory, and XREG/SFR registers. It
is responsible for performing arbitration and sequencing between simultaneous memory accesses to the same
physical memory.
The 8-KB SRAM maps to the DATA memory space and to parts of the XDATA memory spaces. The 8-KB
SRAM is an ultralow-power SRAM that retains its contents even when the digital part is powered off (power
modes 2 and 3). This is an important feature for low-power applications.
The 32/64/128/256 KB flash block provides in-circuit programmable non-volatile program memory for the
device, and maps into the CODE and XDATA memory spaces. In addition to holding program code and
constants, the non-volatile memory allows the application to save data that must be preserved such that it is
available after restarting the device. Using this feature one can, e.g., use saved network-specific data to avoid
the need for a full start-up and network find-and-join process .
Clocks and Power Management
The digital core and peripherals are powered by a 1.8-V low-dropout voltage regulator. It provides power
management functionality that enables low power operation for long battery life using different power modes.
Five different reset sources exist to reset the device.
Peripherals
The CC2530 includes many different peripherals that allow the application designer to develop advanced
applications.
The debug interface implements a proprietary two-wire serial interface that is used for in-circuit debugging.
Through this debug interface, it is possible to perform an erasure of the entire flash memory, control which
oscillators are enabled, stop and start execution of the user program, execute supplied instructions on the 8051
core, set code breakpoints, and single-step through instructions in the code. Using these techniques, it is
possible to perform in-circuit debugging and external flash programming elegantly.
The device contains flash memory for storage of program code. The flash memory is programmable from the
user software and through the debug interface. The flash controller handles writing and erasing the embedded
flash memory. The flash controller allows page-wise erasure and 4-bytewise programming.
The I/O controller is responsible for all general-purpose I/O pins. The CPU can configure whether peripheral
modules control certain pins or whether they are under software control, and if so, whether each pin is configured
as an input or output and if a pullup or pulldown resistor in the pad is connected. CPU interrupts can be enabled
on each pin individually. Each peripheral that connects to the I/O pins can choose between two different I/O pin
locations to ensure flexibility in various applications.
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