ADS8555_14 Datasheet, PDF(20/37 Page) Texas Instruments – 16-Bit, Six-Channel, Simultaneous Sampling ANALOG-TO-DIGITAL CONVERTER

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ADS8555_14 Datasheet, PDF (20/37 Pages) Texas Instruments – 16-Bit, Six-Channel, Simultaneous Sampling ANALOG-TO-DIGITAL CONVERTER

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ADS8555

SBAS531B â DECEMBER 2010 â REVISED FEBRUARY 2011

BUSY/INT

The BUSY signal indicates if a conversion is in

progress. It goes high with a rising edge of any

CONVST_x signal and goes low when the output

data of the last channel pair are available in the

respective output register. The readout of the data

can be initiated immediately after the falling edge of

BUSY.

In sequential mode, the BUSY signal goes low only

for one clock cycle. See the Sequential Mode section

for more details.

The INT output goes high upon completion of a

conversion process and remains high after first read

data access.

The polarity of the BUSY/INT signal can be changed

using CR bit C20.

Reference

The ADS8555 provides an internal, low-drift 2.5V

reference source. To increase the input voltage

range, the reference voltage can be switched to 3V

mode using the VREF bit (bit C18 in the CR). The

reference feeds a 10-bit string-DAC controlled by bits

C[9:0] in the control register. The buffered DAC

output is connected to the REFIO pin. In this way, the

voltage at this pin is programmable in 2.44mV

(2.92mV in 3V mode) steps and adjustable to the

application needs without additional external

components. The actual output voltage can be

calculated using Equation 3:

Range Â´ (Code + 1)

VREF =

1024

Where:

Range = the chosen maximum reference voltage

output range (2.5V or 3V).

Code = the decimal value of the DAC register

content.

(3)

www.ti.com

Table 1 lists some examples of internal reference

DAC settings with a reference range set to 2.5V.

However, to ensure proper performance, the DAC

output voltage should not be programmed below

0.5V.

The buffered output of the DAC should be decoupled

with a 100nF capacitor (minimum); for best

performance, a 470nF capacitor is recommended. If

the internal reference is placed into power-down

(default), an external reference voltage can drive the

REFIO pin.

The voltage at the REFIO pin is buffered with three

internal amplifiers, one for each ADC pair. The output

of each buffer needs to be decoupled with a 10Î¼F

capacitor between pin pairs 53 and 54, 55 and 56,

and 57 and 58. The 10Î¼F capacitors are available as

ceramic 0805-SMD components and in X5R quality.

The internal reference buffers can be powered down

to decrease the power dissipation of the device. In

this case, external reference drivers can be

connected to REFC_A, REFC_B, and REFC_C pins.

With 10Î¼F decoupling capacitors, the minimum

required bandwidth can be calculated using

Equation 4:

ln(2)

f-3dB = 2p Â´ tCONV

(4)

With the minimum tCONV of 1.26Î¼s, the external

reference buffers require a minimum bandwidth of

88kHz.

Table 1. DAC Setting Examples (2.5V Operation)

VREF OUT

(V)

0.500

1.25

2.500

DECIMAL

CODE

204

511

1023

BINARY

CODE

00 1100 1100

01 1111 1111

11 1111 1111

HEXADECIMAL

CODE

1FF

3FF

Product Folder Link(s): ADS8555

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