TNETE110A Datasheet, PDF (2/24 Pages) Texas Instruments – PCI ETHERNETE CONTROLLER SINGLE-CHIP 10 BASE-T

ThunderLAN™ TNETE110A
PCI ETHERNET™ CONTROLLER
SINGLE-CHIP 10 BASE-T
SPWS022A – APRIL 1996 – REVISED NOVEMBER 1996
description
ThunderLAN is a high-speed networking architecture that provides a complete PCI-to-10 Base-T/AUI Ethernet
solution. The TNETE110A, one implementation of the ThunderLAN architecture, is an intelligent protocol
network interface. The ThunderLAN SRAM FIFO-based architecture eliminates the need for external memory
and offers a single-chip glueless PCI-to-10 Base-T/AUI (IEEE 802.3) solution with an on-board physical layer
interface. See Figure 1.
The glueless PCI interface supports 32-bit streaming, operates at speeds up to 33 MHz and is capable of
internal data-transfer rates up to 2 Gbps, taking full advantage of all available PCI bandwidth. The TNETE110A
offers jumperless autoconfiguration using PCI configuration read / write cycles. Customizable configuration
registers, which can be autoloaded from an external serial EEPROM, allow designers of TNETE110A-based
systems to give their systems a unique identification code. The TNETE110A PCI interface, developed in
conjunction with other leaders in the semiconductor and computer industries, has been vigorously tested on
multiple platforms to ensure compatibility across a wide array of available PCI products. In addition, the
ThunderLAN drivers and ThunderLAN architecture use TI’s patented adaptive performance optimization (APO)
technology to dynamically adjust critical parameters for minimum latency, minimum host CPU utilization, and
maximum system performance. This technology ensures that the maximum capabilities of the PCI interface are
used by automatically tuning the adapter to the specific system in which it is operating.
An intelligent protocol handler (PH) implements the serial protocols of the network. The PH is designed for
minimum overhead related to multiple protocols, using common state machines to implement 95 percent of the
total protocol handler. On transmit, the PH serializes data, adds framing and cyclic redundancy check (CRC)
fields, and interfaces to the network physical layer (PHY) chip. On receive, it provides address recognition, CRC
and error checking, frame disassembly, and deserialization. Data for multiple channels is passed to and from
the PH by way of circular-buffer FIFOs in the FIFO SRAM.
Compliant with IEEE Standard 1149.1, the TNETE110A provides a 5-pin test-access port that is used for
boundary-scan testing.
The TNETE110A is available in a 144-pin quad flat package and thin quad flat package.
differences between TNETE110 and TNETE110A:
The TNETE110A implements the CIS pointer register as defined in the PC card standard. This register can be
found in the PCI configuration registers at offset 28h. For other differences between the TNETE110 and
TNETE110A, consult the ThunderLAN Programmer’s Guide (literature number SPWU013).
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