TNETE110A Datasheet, PDF (1/24 Pages) Texas Instruments – PCI ETHERNETE CONTROLLER SINGLE-CHIP 10 BASE-T

D Single-Chip Ethernet™ Adapter for the
Peripheral Component Interconnect (PCI)
Local Bus
– 32-Bit PCI^† Glueless Host Interface
– Compliant With PCI Local-Bus
Specification (Revision 2.0)
– 33-MHz Operation
– 3-V or 5-V I/O Operation
– Adaptive Performance Optimization™
(APO) by Texas Instruments (TI™) for
Highest Available PCI Bandwidth
– High-Performance Bus Master
Architecture With Byte-Aligning DMA
Controller for Low Host CPU and Bus
Utilization
– Plug-and-Play Compatible
D Supports 32-Bit Data Streaming on PCI Bus
– Time Division Multiplexed SRAM
– 2-Gbps Internal Bandwidth
D Driver Compatible With All Previous
ThunderLAN Components
D Switched-Ethernet Compatible
D Full-Duplex Compatible With Independent
Transmit and Receive Channels
D No On-Board Memory Required
D Auto-Negotiation (N-Way) Compatible
D Supports the Card Bus CIS Pointer
Register
ThunderLAN™ TNETE110A
PCI ETHERNET™ CONTROLLER
SINGLE-CHIP 10 BASE-T
SPWS022A – APRIL 1996 – REVISED NOVEMBER 1996
D Integrated 10 Base-T, and 10 Base-5
Attachment Unit Interface (AUI) Physical
Layer Interface
– Single-Chip IEEE 802.3 and Blue Book
Ethernet-Compliant Solution
– DSP-Based Digital Phase-Locked Loop
– Smart Squelch Allows for Transparent
Link Testing
– Transmission Waveshaping
– Autopolarity (Reverse Polarity
Correction)
– External/Internal Loopback Including
Twisted Pair and AUI
– 10 Base-2 Supported Via AUI Interface
D Low-Power CMOS Technology
– Green PC Compatible
– Microsoft™ Advanced Power
Management
D EEPROM Interface Supports Jumperless
Design and Autoconfiguration
D Hardware Statistics Registers for
Management Information Base (MIB)
D DMTF (Desktop Management Task Force)
Compatible
D IEEE Standard 1149.1^‡ Test Access Port
(JTAG)
D 144-Pin Quad Flat Packages (PCM Suffix)
and Thin Quad Flat Packages (PGE Suffix)
10 Base-T
FIFO
10 Base-T
Ethernet
Registers
Physical
PCI
Bus
PCI
Bus Master
Control
Multiplexed
Ethernet
LAN
Controller
10 Mbps
Layer
Interface
10 Base-5
(AUI)
SRAM
FIFO
Figure 1. ThunderLAN Architecture
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
† _{The PCI Local-Bus Specification, Revision 2.0 should be used as a reference with this document.}
‡ _{IEEE Standard 1149.1–1990, IEEE Standard Test-Access Port and Boundary-Scan Architecture}
ThunderLAN, Adaptive Performance Optimization, and TI are trademarks of Texas Instruments Incorporated.
Ethernet is a trademark of Xerox Corporation.
Microsoft is a trademark of Microsoft Corporation.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
Copyright © 1996, Texas Instruments Incorporated
• POST OFFICE BOX 1443 HOUSTON, TEXAS 77251–1443
1