SN74LVT18504 Datasheet, PDF (2/32 Pages) Texas Instruments – 3.3-V ABT SCAN TEST DEVICE WITH 20-BIT UNIVERSAL BUS TRANSCEIVERS

SN74LVT18504
3.3ĆV ABT SCAN TEST DEVICE
WITH 20ĆBIT UNIVERSAL BUS TRANSCEIVERS
SCBS163F − AUGUST 1993 − REVISED JULY 1996
description
The SN74LVT18504 scan test device with 20-bit universal bus transceivers is a member of the Texas
Instruments SCOPE  testability integrated circuit family. This family of devices supports IEEE
Standard 1149.1-1990 boundary scan to facilitate testing of complex circuit-board assemblies. Scan access to
the test circuitry is accomplished via the 4-wire test access port (TAP) interface.
Additionally, this device is designed specifically for low-voltage (3.3-V) V_CC operation, but with the capability
to provide a TTL interface to a 5-V system environment.
In the normal mode, this device is a 20-bit universal bus transceiver that combines D-type latches and D-type
flip-flops to allow data flow in transparent, latched, or clocked modes. The test circuitry can be activated by the
TAP to take snapshot samples of the data appearing at the device pins or to perform a self test on the
boundary-test cells. Activating the TAP in the normal mode does not affect the functional operation of the
SCOPE universal bus transceivers.
Data flow in each direction is controlled by output-enable (OEAB and OEBA), latch-enable (LEAB and LEBA),
clock-enable (CLKENAB and CLKENBA), and clock (CLKAB and CLKBA) inputs. For A-to-B data flow, the
device operates in the transparent mode when LEAB is high. When LEAB is low, the A-bus data is latched while
CLKENAB is high and/or CLKAB is held at a static low or high logic level. Otherwise, if LEAB is low and
CLKENAB is low, A-bus data is stored on a low-to-high transition of CLKAB. When OEAB is low, the B outputs
are active. When OEAB is high, the B outputs are in the high-impedance state. B-to-A data flow is similar to
A-to-B data flow but uses the OEBA, LEBA, CLKENBA, and CLKBA inputs.
In the test mode, the normal operation of the SCOPE  universal bus transceivers is inhibited and the test
circuitry is enabled to observe and control the I/O boundary of the device. When enabled, the test circuitry
performs boundary-scan test operations according to the protocol described in IEEE Standard 1149.1-1990.
Four dedicated test pins are used to observe and control the operation of the test circuitry: test data input (TDI),
test data output (TDO), test mode select (TMS), and test clock (TCK). Additionally, the test circuitry performs
other testing functions such as parallel-signature analysis (PSA) on data inputs and pseudo-random pattern
generation (PRPG) from data outputs. All testing and scan operations are synchronized to the TAP interface.
Active bus-hold circuitry is provided to hold unused or floating data inputs at a valid logic level.
The SN74LVT18504 is characterized for operation from − 40°C to 85°C.
FUNCTION TABLE†
(normal mode, each register)
INPUTS
OUTPUT
OEAB LEAB CLKENAB CLKAB A
B
L
L
L
L
X
B0‡
L
L
L
↑
L
L
L
L
L
L
L
H
L
H
X
↑
H
H
X
X
B0‡
X
L
L
L
H
X
X
H
H
H
X
X
X
X
Z
† _{A-to-B data flow is shown. B-to-A data flow is similar but uses OEBA,}
LEBA, CLKENBA, and CLKBA.
‡ _{Output level before the indicated steady-state input conditions were}
established
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