SN74LVC573A-EP Datasheet, PDF (2/9 Pages) Texas Instruments – OCTAL TRANSPARENT D-TYPE LATCH WITH 3-STATE OUTPUTS

SN74LVC573A-EP
OCTAL TRANSPARENT D-TYPE LATCH
WITH 3-STATE OUTPUTS
SCAS749A – DECEMBER 2003 – REVISED AUGUST 2005
www.ti.com
DESCRIPTION/ORDERING INFORMATION (CONTINUED)
A buffered output-enable (OE) input can be used to place the eight outputs in either a normal logic state (high or
low logic levels) or the high-impedance state. In the high-impedance state, the outputs neither load nor drive the
bus lines significantly. The high-impedance state and increased drive provide the capability to drive bus lines
without interface or pullup components.
OE does not affect the internal operations of the latches. Old data can be retained or new data can be entered
while the outputs are in the high-impedance state.
This device is fully specified for partial-power-down applications using I_off. The I_off circuitry disables the outputs,
preventing damaging current backflow through the device when it is powered down.
To ensure the high-impedance state during power up or power down, OE should be tied to V_CC through a pullup
resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.
Inputs can be driven from either 3.3-V or 5-V devices. This feature allows the use of this device as a translator in
a mixed 3.3-V/5-V system environment.
FUNCTION TABLE
(EACH LATCH)
INPUTS
OE
LE
D
L
H
H
L
H
L
L
L
X
H
X
X
OUTPUT
Q
H
L
Q₀
Z
OE ¹
LOGIC DIAGRAM (POSITIVE LOGIC)
LE ¹¹
C1
2
1D
1D
19
1Q
To Seven Other Channels
2