SN74LVC573A-EP Datasheet, PDF (1/9 Pages) Texas Instruments – OCTAL TRANSPARENT D-TYPE LATCH WITH 3-STATE OUTPUTS

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FEATURES
• Controlled Baseline
– One Assembly/Test Site, One Fabrication
Site
• Extended Temperature Performance of –40°C
to 125°C
• Enhanced Diminishing Manufacturing
Sources (DMS) Support
• Enhanced Product-Change Notification
• Qualification Pedigree ⁽¹⁾
• Operates From 2 V to 3.6 V
• Inputs Accept Voltages to 5.5 V
• Max t_pd of 6.9 ns at 3.3 V
• Typical V_OLP (Output Ground Bounce) <0.8 V
at V_CC = 3.3 V, T_A = 25°C
• Typical V_OHV (Output V_OH Undershoot) >2 V at
V_CC = 3.3 V, T_A = 25°C
(1) Component qualification in accordance with JEDEC and
industry standards to ensure reliable operation over an
extended temperature range. This includes, but is not limited
to, Highly Accelerated Stress Test (HAST) or biased 85/85,
temperature cycle, autoclave or unbiased HAST,
electromigration, bond intermetallic life, and mold compound
life. Such qualification testing should not be viewed as
justifying use of this component beyond specified
performance and environmental limits.
SN74LVC573A-EP
OCTAL TRANSPARENT D-TYPE LATCH
WITH 3-STATE OUTPUTS
SCAS749A – DECEMBER 2003 – REVISED AUGUST 2005
• Supports Mixed-Mode Signal Operation on All
Ports (5-V Input/Output Voltage With 3.3-V
V_CC)
• I_off Supports Partial-Power-Down Mode
Operation
DW OR PW PACKAGE
(TOP VIEW)
OE 1
1D 2
2D 3
3D 4
4D 5
5D 6
6D 7
7D 8
8D 9
GND 10
20 V_CC
19 1Q
18 2Q
17 3Q
16 4Q
15 5Q
14 6Q
13 7Q
12 8Q
11 LE
DESCRIPTION/ORDERING INFORMATION
The SN74LVC573A-EP octal transparent D-type latch is designed for 2.7-V to 3.6-V V_CC operation.
This device features 3-state outputs designed specifically for driving highly capacitive or relatively low-impedance
loads. It is particularly suitable for implementing buffer registers, input/output (I/O) ports, bidirectional bus drivers,
and working registers.
While the latch-enable (LE) input is high, the Q outputs follow the data (D) inputs. When LE is taken low, the Q
outputs are latched at the logic levels at the D inputs.
T_A
–40°C to 125°C
SOIC – DW
TSSOP – PW
ORDERING INFORMATION
PACKAGE ⁽¹⁾
ORDERABLE PART NUMBER
Reel of 2000
SN74LVC573AQDWREP
Reel of 2000
SN74LVC573AQPWREP
TOP-SIDE MARKING
C573AEP
C573AEP
(1) Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are available at
www.ti.com/sc/package.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2003–2005, Texas Instruments Incorporated