SN74AUP1T14_15 Datasheet, PDF (2/14 Pages) Texas Instruments – LOW POWER, 1.8/2.5/3.3-V INPUT, 3.3-V CMOS OUTPUT, SINGLE SCHMITT-TRIGGER INVERTER GATE

SN74AUP1T14
SCES802 – APRIL 2010
www.ti.com
T_A
–40°C to 85°C
ORDERING INFORMATION⁽¹⁾
PACKAGE ⁽²⁾
ORDERABLE PART NUMBER
Reel of 3000
SOT (SC-70) – DCK
Reel of 250
SN74AUP1T14DCKR
SN74AUP1T14DCKT
TOP-SIDE MARKING⁽³⁾
6F_
(1) For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI
web site at www.ti.com.
(2) Package drawings, thermal data, and symbolization are available at www.ti.com/packaging.
(3) The actual top-side marking has one additional character that designates the wafer fab/assembly site.
FUNCTION TABLE
INPUT
(Lower Level Input)
A
OUTPUT
(V_CC CMOS)
Y
H
L
L
H
Supply V_CC = 2.3 V to 2.7 V (2.5 V)
INPUTS
V_T+ max = V_IH min
V_T- min = V_IL max
OUTPUT
CMOS
A
B
Y
V_IH = 1.1 V
V_IL = 0.35 V
V_OH = 1.85 V
V_OL = 0.45 V
Supply V_CC = 3 V to 3.6 V (3.3 V)
INPUTS
V_T+ max = V_IH min
V_T- min = V_IL max
OUTPUT
CMOS
A
B
Y
V_IH = 1.19 V
V_IL = 0.5 V
V_OH = 2.55 V
V_OL = 0.45 V
LOGIC DIAGRAM (SCHMITT-TRIGGER INVERTER GATE)
A²
4_Y
Static-Power Consumption
(µA)
100%
Dynamic-Power Consumption
(pF)
100%
80%
80%
60%
40%
3.3-V
Logic^†
60%
40%
L³V^.3C^-V
Logic^†
20%
0%
AUP
20%
0%
† _{Single, dual, and triple gates}
AUP
Figure 1. AUP – The Lowest-Power Family
Switching Characteristics
at 25 MHz^†
3.5
3
2.5
2 Input
1.5
1
Output
0.5
0
−0.5 _{0 5 10 15 20 25 30 35 40 45}
Time − ns
† _{AUP1G08 data at CL = 15 pF}
Figure 2. Excellent Signal Integrity
2
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