SM74202 Datasheet, PDF (2/12 Pages) Texas Instruments – 100V Current Mode PWM Controller

SM74202
SNOSBA4A – NOVEMBER 2011 – REVISED APRIL 2013
Connection Diagram
1
VIN
2
FB
3
COMP
4
VCC
5
OUT
10
SS
9
RT/SYNC
8
CS
7
UVLO
6
GND
Figure 2. 10-Lead VSSOP, WSON
Package Number DGS0010A
Top View
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PIN DESCRIPTIONS
Pin
Name
Description
Application Information
1
VIN
Source Input Voltage
Input to the start-up regulator. Input range is 13V to 100V.
2
FB
Feedback Signal
Inverting input of the internal error amplifier. The non-
inverting input is internally connected to a 1.25V reference.
3
COMP The output of the error amplifier and input to the COMP pull-up is provided by an internal 5K resistor which
Pulse Width Modulator
may be used to bias an opto-coupler transistor.
4
VCC
Output of the internal high voltage series pass
If an auxiliary winding raises the voltage on this pin above
regulator. Regulated output voltage is 7.7V
the regulation set point, the internal series pass regulator
will shut down, reducing the internal power dissipation.
5
OUT
Output of the PWM controller
Gate driver output with a 1A peak current capability.
6
GND
Ground return
7
UVLO Line Under-Voltage Shutdown
An external resistor divider from the power converter
source voltage sets the shutdown levels. The threshold at
this pin is 1.25V. Hysteresis is set by a switched internal
20µA current source.
8
CS
Current Sense input
Current sense input for current mode control and over-
current protection. Current limiting is accomplished using a
dedicated current sense comparator. If the CS pin voltage
exceeds 0.5V the OUT pin switches low for cycle-by-cycle
current limiting. CS is held low for 50ns after OUT switches
high to blank leading edge current spikes.
9
RT / SYNC Oscillator timing resistor pin and synchronization An external resistor connected from RT to GND sets the
input
oscillator frequency. This pin also accepts synchronization
pulses from an external clock.
10
SS
Softstart Input
An external capacitor and an internal 10µA current source
set the soft-start ramp rate.
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
2
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