ONET8531T_16 Datasheet, PDF (2/17 Pages) Texas Instruments – 11.3 Gbps Limiting Transimpedance Amplifier

ONET8531T
SLLS891B – FEBRUARY 2008 – REVISED AUGUST 2011
www.ti.com
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
BLOCK DIAGRAM
Figure 1 shows an ONET8531T block diagram. The ONET8531T consists of the signal path, supply filters, a
control block for DC input bias, automatic gain control (AGC), and a received signal strength indicator (RSSI).
The RSSI provides the bias for the TIA stage and the control for the AGC.
The signal path consists of a transimpedance amplifier stage, a voltage amplifier, and a CML output buffer. The
on-chip filter circuit provides a filtered V_CC for the PIN photodiode and for the transimpedance amplifier.
The DC input bias circuit and automatic gain control use internal low pass filters to cancel the DC current on the
input and to adjust the transimpedance amplifier gain. Additionally, the chip provides circuitry to monitor the
received signal strength.
VCC_OUT
VCC_IN
To Voltage Amplifier and Output Buffer
To TIA
GND
FILTER1/2
220 W
RF
AGC and DC
Offset
Cancellation
RSSI_IB
OUT+
IN
OUT-
TIA
Voltage Amplifier
CML Output Buffer
Figure 1. ONET8531T Block Diagram
RSSI_EB
2
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