MCM28F256ACH Datasheet, PDF (2/14 Pages) Texas Instruments – 256-Mbit (32-Mbit x 8, 16-Mbit x 16) Flash Memory Module with Internal Decoding and Boundary Scan I/O Buffers

PRELIMINARY
July 1995
MCM28F256ACH
256-Mbit (32-Mbit x 8 16-Mbit x 16) Flash Memory Module
with Internal Decoding and Boundary Scan I O Buffers
General Description
Features
The MCM28F256ACH is a 268 435 456-bit flash memory
module organized as 16 pages with 16 777 216 bytes
(8 388 608 words) per page Utilizing Intel’s FlashFile^TM
Y _{Read access time of 140 ns over the industrial temper-}
ature range (160 ns over the military temperature
range)
Memory and National’s SCAN^TM I O buffers the ^Y Utilizes Intel’s FlashFile architecture with 512 indepen-
MCM28F256ACH offers several revolutionary features in-
dently lockable blocks (16 pages with 32 blocks per
cluding a user-configurable x8 x16 architecture selective
block locking on-board write buffers pipelined command
execution and boundary scan test capability Several power
reduction features are also incorporated including Automat-
ic Power Savings (APS) which puts the module into a low
current state when it is being accessed by a slowed or
stopped CPU
The MCM28F256ACH includes sixteen 28F016SA flash
te ^{memories decoding logic and IEEE 1149 1 compliant I O}
buffers The module is offered in a 68-lead hermetic pack-
age Both through-hole and surface mount lead configura-
tions are available
Obsole ^{Connection Diagram}
page)
Y _{Choice of x8 or x16 architecture (user-configurable)}
Y _{Pipelined command execution}
Y _{Automated write and erase capability can be executed}
simultaneously in all 16 pages greatly improving aver-
age write erase cycle times
Y _{National’s lEEE 1149 1 compliant SCAN I O buffers}
simplify the integration of design and test
Y _{TTL compatible inputs}
Y _{Low noise TRl-STATE outputs drive 50X transmission}
line to TTL levels (75X transmission line over military
temperature range)
Y _{Hermetically sealed integral substrate package}
Y _{DIP and surface mount packaging available}
Pin
Names
A₀
A₁ – A₂₄
DQ₀ – DQ₇
DQ₈ – DQ₁₅
CE
RP
OE
WE
RY BY
WP
BYTE
V_PP
V_CC
GND
NC
Description
Byte-Select Address Input
Word-Select Address Inputs
Low-Byte Data I O Bus
High-Byte Data I O Bus
Chip Enable Input (Active LOW)
Reset Power-Down Input (Active LOW)
Output Enable Input (Active LOW)
Write Enable Input (Active LOW)
Ready Busy Output
Write Protect Input (Active LOW)
Byte Enable Input (Active LOW)
Erase Write Power Supply
Device Power Supply
Ground
No Connection
TL Z 12436 – 1
TRI-STATE is a registered trademark of National Semiconductor Corporation
SCANTM is a trademark of National Semiconductor Corporation
FlashFileTM is a trademark of Intel Corporation
C1995 National Semiconductor Corporation TL Z 12436
RRD-B30M115 Printed in U S A