LP38512-ADJ Datasheet, PDF (2/24 Pages) National Semiconductor (TI) – 1.5A Fast-Transient Response Adjustable Low-Dropout Linear Voltage Regulator

LP38512-ADJ
SNVS546D – JANUARY 2009 – REVISED APRIL 2013
Connection Diagram
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EN 1
IN 2
GND 3
OUT 4
ADJ 5
Exposed
DAP
Figure 1. 5-Pin PFM, Top View
See NDQ0005A Package
OUT 1
OUT 2
ADJ 3
N/C 4
8 IN
7 IN
6 EN
5 GND
DAP
Connect to GND
Figure 2. 8-Pin SO PowerPad, Top View
See DDA0008A Package
Pin #
1
2
3
4
5
DAP
Pin Name
EN
IN
GND
OUT
ADJ
DAP
PIN DESCRIPTIONS FOR PFM PACKAGE
Function
Enable. Pull high to enable the output, low to disable the output. This pin has no internal bias and
must be tied to the input voltage, or actively driven.
Input Supply Pin
Ground
Regulated Output Voltage Pin
The feedback to the internal Error Amplifier to set the output voltage
The PFM DAP is used as a thermal connection to remove heat from the device to an external heat-
sink in the form of the copper area on the printed circuit board. The DAP is physically connected to
backside of the die, but is not internally connected to device ground. The DAP should be soldered to
the Ground Plane copper.
Pin #
1, 2
3
4
5
6
7, 8
DAP
Pin Name
OUT
ADJ
N/C
GND
EN
IN
DAP
PIN DESCRIPTIONS FOR SO PowerPad PACKAGE
Function
Regulated Output Voltage Pin. Pins share current and must be connected together.
The feedback to the internal Error Amplifier to set the output voltage
No internal connection.
Ground
Enable. Pull high to enable the output, low to disable the output. This pin has no internal bias and
must be tied to the input voltage, or actively driven.
Input Supply Pin. Pins share current and must be connected together.
TheSO PowerPad DAP connection is used as a thermal connection to remove heat from the device
to an external heat-sink in the form of the copper area on the printed circuit board. The DAP is
physically connected to backside of the die, but is not internally connected to device ground. The
DAP should be soldered to the Ground Plane copper.
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
2
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