CY74FCT825T_14 Datasheet, PDF (2/14 Pages) Texas Instruments – 8-BIT BUS-INTERFACE REGISTER WITH 3-STATE OUTPUTS

CY74FCT825T
8-BIT BUS-INTERFACE REGISTER
WITH 3-STATE OUTPUTS
SCCS070A – OCTOBER 2001 – REVISED NOVEMBER 2001
PIN DESCRIPTION
NAME I/O
DESCRIPTION
D
I
D flip-flop data inputs
CLR
I
When CLR is low and OE is low, Q outputs are low. When CLR is high, data can be entered into the register.
CP
O Clock pulse for the register. Enters data into the register on the low-to-high clock transition.
Y
O Register 3-state outputs
EN
I
Clock enable. When EN is low, data on the D input is transferred to the Q output on the low-to-high clock transition. When
EN is high, the Q outputs do not change state, regardless of the data or clock input transitions.
OE
I
Output control. When OE is high, the Y outputs are in the high-impedance state. When OE is low, true register data is present
at the Y outputs.
FUNCTION TABLE
INPUTS
OE CLR EN
D
INTERNAL
OUTPUTS
FUNCTION
CP
Q
Y
H
H
L
L
↑
L
Z
Z
H
H
L
H
↑
H
Z
H
L
X
X
X
L
Z
L
L
X
X
X
L
L
Clear
H
H
H
X
X
NC
Z
L
H
H
X
X
NC NC
Hold
H
H
L
L
↑
L
Z
H
H
L
H
↑
H
Z
L
H
L
L
↑
L
L
Load
L
H
L
H
↑
H
H
H = High logic level, L = Low logic level, X = Don’t care, NC = No change,
↑ = Low-to-high transition, Z = High-impedance state
logic diagram (positive logic)
1
OE1
OE2
2
OE3 ²³
11
CLR
13
CP
14
EN
3
D0
CL
CP _Q
D
22 _Y0
To Seven Other Channels
2
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