CD74HC125-Q1 Datasheet, PDF (2/13 Pages) Texas Instruments – HIGH-SPEED CMOS LOGIC QUAD BUFFER WITH 3-STATE OUTPUTS

CD74HC125-Q1
HIGH-SPEED CMOS LOGIC
QUAD BUFFER WITH 3-STATE OUTPUTS
SCLS579A − APRIL 2004 − REVISED SEPTEMBER 2008
logic diagram (positive logic)
1OE ¹
2
1A
3
1Y
2OE ⁴
5
2A
6
2Y
3OE ¹⁰
9
3A
4OE ¹³
12
4A
8
3Y
11
4Y
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)^†
Supply voltage range, V_CC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to 7 V
Input clamp current, I_IK (V_I < −0.5 V or V_I > V_CC + 0.5 V) (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . ±20 mA
Output clamp current, I_OK (V_O < −0.5 V or V_O > V_CC + 0.5 V) (see Note 1) . . . . . . . . . . . . . . . . . . . . . ±20 mA
Continuous output current, I_O (V_O > −0.5 or V_O < V_CC + 0.5 V) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±35 mA
Output source or sink current per output pin, I_O (V_O > −0.5 or V_O < V_CC + 0.5 V) . . . . . . . . . . . . . . . . ±25 mA
Continuous current through V_CC or GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±70 mA
Package thermal impedance, θ_JA (see Note 2): M package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86°C/W
PW package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113°C/W
Storage temperature range, T_stg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −65°C to 150°C
† _{Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and}
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES: 1. The input and output voltage ratings may be exceeded if the input and output current ratings are observed.
2. The package thermal impedance is calculated in accordance with JESD 51-7.
recommended operating conditions (see Note 3)
MIN NOM MAX UNIT
V_CC
Supply voltage
2
5
6V
V_CC = 2 V
1.5
V_IH
High-level input voltage
V_CC = 4.5 V
3.15
V
V_CC = 6 V
4.2
V_CC = 2 V
0.5
V_IL
Low-level input voltage
V_CC = 4.5 V
1.35 V
V_CC = 6 V
1.8
V_I
Input voltage
0
V_CC
V
V_O
Output voltage
0
V_CC
V
V_CC = 2 V
1000
t_t
Input transition rise/fall time
V_CC = 4.5 V
500 ns
V_CC = 6 V
400
T_A
Operating free-air temperature
−40
125 °C
NOTE 3: All unused inputs of the device must be held at V_CC or GND to ensure proper device operation. Refer to the TI application report,
Implications of Slow or Floating CMOS Inputs, literature number SCBA004.
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