BQ3285_15 Datasheet, PDF (2/26 Pages) Texas Instruments – Real-Time Clock (RTC)

bq3285
Block Diagram
Pin Descriptions
MOT
Bus type select input
MOT selects bus timing for either Motorola
or Intel architecture. This pin should be
tied to VCC for Motorola timing or to VSS for
Intel timing (see Table 1). The setting
should not be changed during system opera-
tion. MOT is internally pulled low by a
30KΩ resistor.
Table 1. Bus Setup
Bus MOT
DS
R/W
AS
Type Level Equivalent Equivalent Equivalent
DS, E, or
Motorola VCC _Φ2
R/W
AS
Intel
RD,
WR,
VSS MEMR, or MEMW, or ALE
I/OR
I/OW
AD0–AD7
AS
Multiplexed address/data input/
output
The bq3285 bus cycle consists of two
phases: the address phase and the data-
transfer phase. The address phase pre-
cedes the data-transfer phase. During the
address phase, an address placed on
AD0–AD7 is latched into the bq3285 on the
falling edge of the AS signal. During the
data-transfer phase of the bus cycle, the
AD0–AD7 pins serve as a bidirectional data
bus.
Address strobe input
AS serves to demultiplex the address/data
bus. The falling edge of AS latches the ad-
dress on AD0–AD7. This demultiplexing pro-
cess is independent of the CS signal. For
DIP a n d SOIC packages with MOT =
VCC, the AS input is provided a signal simi-
lar to ALE in an Intel-based system.
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