SM320C6455-EP Datasheet, PDF (194/254 Pages) Texas Instruments – FIXED-POINT DIGITAL SIGNAL PROCESSOR

SM320C6455-EP
FIXED-POINT DIGITAL SIGNAL PROCESSOR
SPRS462B – SEPTEMBER 2007 – REVISED JANUARY 2008
www.ti.com
Table 7-60. Switching Characteristics Over Recommended Operating Conditions for McBSP
(see Figure 7-52) (continued)
NO.
PARAMETER
3
t_w(CKRX)
4
t_d(CKRH-FRV)
9
t_d(CKXH-FXV)
12
t_{dis(CKXH-DXHZ)}
13
t_d(CKXH-DXV)
14
t_d(FXH-DXV)
Pulse duration, CLKR/X high or CLKR/X low
Delay time, CLKR high to internal FSR valid
Delay time, CLKX high to internal FSX valid
Disable time, DX high impedance following
last data bit from CLKX high
Delay time, CLKX high to DX valid
Delay time, FSX high to DX valid
ONLY applies when in data
delay 0 (XDATDLY = 00b) mode
CLKR/X int
CLKR int
CLKX int
CLKX ext
CLKX int
CLKX ext
CLKX int
CLKX ext
FSX int
FSX ext
-720
-850
A-1000/-1000
-1200
MIN
C – 1⁽⁷⁾
MAX
C + 1⁽⁷⁾
–2.1
3.3
–1.7
3
1.7
9
–3.9
4
2.1
–3.9 + D1⁽⁸⁾
2.1 + D1⁽⁸⁾
–2.3 + D1⁽⁹⁾
9
4 + D2⁽⁸⁾
9 + D2⁽⁸⁾
5.6 + D2⁽⁹⁾
1.9 + D1⁽⁹⁾
9 + D2⁽⁹⁾
UNIT
ns
ns
ns
ns
ns
ns
(7) C = H or L
S = sample rate generator input clock = 6P if CLKSM = 1 (P = 1/CPU clock frequency)
S = sample rate generator input clock = P_clks if CLKSM = 0 (P_clks = CLKS period)
H = CLKX high pulse width = (CLKGDV/2 + 1) * S if CLKGDV is even
H = (CLKGDV + 1)/2 * S if CLKGDV is odd
L = CLKX low pulse width = (CLKGDV/2) * S if CLKGDV is even
L = (CLKGDV + 1)/2 * S if CLKGDV is odd
CLKGDV should be set appropriately to ensure the McBSP bit rate does not exceed the maximum limit (see (4) above).
(8) Extra delay from CLKX high to DX valid applies only to the first data bit of a device, if and only if DXENA = 1 in SPCR.
if DXENA = 0, then D1 = D2 = 0
if DXENA = 1, then D1 = 6P, D2 = 12P
(9) Extra delay from FSX high to DX valid applies only to the first data bit of a device, if and only if DXENA = 1 in SPCR.
if DXENA = 0, then D1 = D2 = 0
if DXENA = 1, then D1 = 6P, D2 = 12P
194 C64x+ Peripheral Information and Electrical Specifications
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