SM320C6455-EP Datasheet, PDF (179/254 Pages) Texas Instruments – FIXED-POINT DIGITAL SIGNAL PROCESSOR

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SM320C6455-EP
FIXED-POINT DIGITAL SIGNAL PROCESSOR
SPRS462B – SEPTEMBER 2007 – REVISED JANUARY 2008
7.12 Host-Port Interface (HPI) Peripheral
7.12.1 HPI Device-Specific Information
The C6455 device includes a user-configurable 16 bit or 32 bit Host-port interface (HPI16/HPI32). The
AEA14 pin controls the HPI_WIDTH, allowing the user to configure the HPI as a 16 bit or 32 bit peripheral.
Software handshaking via the HRDY bit of the Host Port Control Register (HPIC) is not supported on the
C6455.
An HPI boot is terminated using a DSP interrupt. The DSP interrupt is registered in bit 0 (channel 0) of the
EDMA Event Register (ER). This event must be cleared by software before triggering transfers on DMA
channel 0.
7.12.2 HPI Peripheral Register Description(s)
Table 7-54. HPI Control Registers
HEX ADDRESS RANGE
0288 0000
0288 0004
0288 0008 - 0288 0024
0288 0028
0288 002C
0288 0030
0288 0034
0288 0038
0288 000C - 028B 007F
0288 0080 - 028B FFFF
ACRONYM
-
PWREMU_MGMT
-
-
-
HPIC
HPIA
(HPIAW) ⁽²⁾
HPIA
(HPIAR) ⁽²⁾
-
-
Reserved
REGISTER NAME
HPI power and emulation management register
Reserved
Reserved
Reserved
HPI control register
HPI address register
(Write)
HPI address register
(Read)
Reserved
Reserved
COMMENTS
The CPU has read/write
access to the
PWREMU_MGMT register;
the Host does not have any
access to this register.
The Host and the CPU have
read/write access to the
HPIC register.⁽¹⁾
The Host has read/write
access to the HPIA registers.
The CPU has only read
access to the HPIA registers.
(1) The CPU can write 1 to the HINT bit to generate an interrupt to the host and it can write 1 to the DSPINT bit to clear/acknowledge an
interrupt from the host.
(2) There are two 32 bit HPIA registers: HPIAR for read operations and HPIAW for write operations. The HPI can be configured such that
HPIAR and HPIAW act as a single 32 bit HPIA (single-HPIA mode) or as two separate 32 bit HPIAs (dual-HPIA mode) from the
perspective of the host. The CPU can access HPIAW and HPIAR independently. For details about the HPIA registers and their modes,
see the TMS320C645x DSP Host Port Interface (HPI) User's Guide (literature number SPRU969).
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C64x+ Peripheral Information and Electrical Specifications 179