TMS320TCI6484CMH Datasheet, PDF (193/242 Pages) Texas Instruments – Communications Infrastructure Digital Signal Processor

www.ti.com
TMS320TCI6484
Communications Infrastructure Digital Signal Processor
SPRS438E—October 2009
Table 8-80 SPI Timing Requirements as Master or Slave: CLKSTP = 10b, CLKXP = 1 ^{(1) (2)}
(see Figure 8-39)
Master
Slave
No.
4 t_su(DRV-CKXH)
5 t_h(CKXH-DRV)
End of Table 8-80
Setup time, DR valid before CLKX high
Hold time, DR valid after CLKX high
Min
Max
Min
Max Unit
12
2-12P
ns
4
5+24P
ns
1 P = 1/SYSREFCLK frequency in ns. For example, when running parts at 1000 MHz, use P = 1 ns.
2 For all SPI Slave modes, CLKG is programmed as 1/6 of the CPU clock by setting CLKSM = CLKGDV = 1.
Table 8-81 SPI Switching Characteristics as Master or Slave: CLKSTP = 10b, CLKXP = 1 ^{(1) (2) (3) (4) (5)}
(see Figure 8-39)
Master
Slave
No.
1 t_d(CKXH-FXH)
2 t_d(FXL-CKXL)
3 t_d(CKXL-DXV)
6 t_{dis(CKXH-DXHZ)}
Parameter
Delay time, FSX high after CLKX high
Delay time, CLKX low after FSX low
Delay time, CLKX low to DX valid
Disable time, DX high impedance following last data bit from
CLKX high
Min
Max
Min
Max Unit
T-2
T+3
ns
H-3
H+3
ns
-2
4 12P + 2.8 24P + 17 ns
H-2
H+3
ns
7 t_{dis(FXH-DXHZ)}
Disable time, DX high impedance following last data bit from
FSX high
4P+3 12P+17 ns
8 t_d(FXL-DXV)
End of Table 8-81
Delay time, FSX low to DX valid
8P+2 18P+17 ns
1 P = 1/SYSREFCLK frequency in ns. For example, when running parts at 1000 MHz, use P = 1 ns.
2 For all SPI Slave modes, CLKG is programmed as 1/6 of the CPU clock by setting CLKSM = CLKGDV = 1.
3 S = Sample rate generator input clock = 6P if CLKSM = 1
S = Sample rate generator input clock = P_clks if CLKSM = 0 (P_clks = CLKS period)
T = CLKX period = (1 + CLKGDV) * S
H = CLKX high pulse width = (CLKGDV/2 + 1) * S if CLKGDV is even
H = (CLKGDV + 1)/2 * S if CLKGDV is odd
L = CLKX low pulse width = (CLKGDV/2) * S if CLKGDV is even
L = (CLKGDV + 1)/2 * S if CLKGDV is odd
4 FSRP = FSXP = 1. As a SPI Master, FSX is inverted to provide active-low slave-enable output. As a Slave, the active-low signal input on FSX and FSR is inverted before being
used internally.
CLKXM = FSXM = 1, CLKRM = FSRM = 0 for Master McBSP
CLKXM = CLKRM = FSXM = FSRM = 0 for Slave McBSP
5 FSX should be low before the rising edge of clock to enable Slave devices and then begin a SPI transfer at the rising edge of the Master clock (CLKX).
Figure 8-39 SPI Timing as Master or Slave: CLKSTP = 10b, CLKXP = 1
CLKX
1
FSX
7
6
DX
Bit 0
DR
Bit 0
2
8
4
Bit(n-1)
Bit(n-1)
3
(n-2)
5
(n-2)
(n-3)
(n-3)
(n-4)
(n-4)
Copyright © 2009 Texas Instruments Incorporated
C64x+ Peripheral Information and Electrical Specifications 193