TMS320C6745_13 Datasheet, PDF (192/227 Pages) Texas Instruments – TMS320C6745,TMS320C6747 Fixed/Floating-Point Digital Signal Processor

TMS320C6745, TMS320C6747
SPRS377E – SEPTEMBER 2008 – REVISED FEBRUARY 2013
www.ti.com
5.27.1 USB2.0 Electrical Data/Timing
The USB PHY PLL can support input clock of the following frequencies: 12.0 MHz, 13.0 MHz, 19.2 MHz,
20.0 MHz, 24.0 MHz, 26.0 MHz, 38.4 MHz, 40.0 MHz or 48.0 MHz. USB_REFCLKIN jitter tolerance is 50
ppm maximum.
C6747 supports low-speed, full-speed and high-speed.
C6745 supports only low-speed and full-speed.
Table 5-97. Switching Characteristics Over Recommended Operating Conditions for USB2.0 (see
Figure 5-66)
No.
PARAMETER
LOW SPEED
1.5 Mbps
FULL SPEED
12 Mbps
MIN MAX MIN MAX
1 t_r(D)
2 t_f(D)
3 t_rfM
4 V_CRS
Rise time, USB0_DP and USB0_DM signals⁽¹⁾
Fall time, USB0_DP and USB0_DM signals⁽¹⁾
Rise/Fall time, matching⁽²⁾
Output signal cross-over voltage⁽¹⁾
75
300
4
20
75
300
4
20
80
120
90
111
1.3
2
1.3
2
5 t_jr(source)NT Source (Host) Driver jitter, next transition
2
2
t_jr(FUNC)NT Function Driver jitter, next transition
6 t_jr(source)PT Source (Host) Driver jitter, paired transition⁽⁴⁾
25
2
1
1
t_jr(FUNC)PT
7 t_w(EOPT)
8 t_w(EOPR)
Function Driver jitter, paired transition
Pulse duration, EOP transmitter ⁽⁵⁾
Pulse duration, EOP receiver ⁽⁵⁾
10
1
1250 1500 160
175
670
82
9 t_(DRATE)
Data Rate
1.5
12
10 Z_DRV
Driver Output Resistance
–
–
40.5 49.5
11 Z_INP
Receiver Input Impedance
100k
100k
(1) Low Speed: C_L = 200 pF, Full Speed: C_L = 50 pF, High Speed: C_L = 50 pF
(2) t_RFM = (t_r/t_f) x 100. [Excluding the first transaction from the Idle state.]
(3) For more detailed information, see the Universal Serial Bus Specification Revision 2.0, Chapter 7. Electrical.
(4) t_jr = t_px(1) - t_px(0)
(5) Must accept as valid EOP
HIGH SPEED
480 Mbps
MIN MAX
0.5
0.5
–
–
–
–
–
–
40.5
-
(3)
(3)
(3)
–
480
49.5
-
UNIT
ns
ns
%
V
(3)_ns
ns
ns
ns
ns
ns
Mb/s
Ω
Ω
USB0_DM
V_CRS
USB0_DP
10% V_OL
t_per - t_jr
90% V_OH
t_r
t_f
Figure 5-66. USB0 Integrated Transceiver Interface Timing
5.27.2 USB0 Unused Signal Configuration
If USB0 is unused, then the USB0 signals should be configured as shown in Section 5.4.
192 Peripheral Information and Electrical Specifications
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