TMS320C6745_13 Datasheet, PDF (140/227 Pages) Texas Instruments – TMS320C6745,TMS320C6747 Fixed/Floating-Point Digital Signal Processor

TMS320C6745, TMS320C6747
SPRS377E – SEPTEMBER 2008 – REVISED FEBRUARY 2013
www.ti.com
Table 5-61. Additional⁽¹⁾ SPI0 Slave Timings, 5-Pin Option^{(2) (3)}
No.
25 t_{d(SCSL_SPC)S}
26 t_{d(SPC_SCSH)S}
27 t_{ena(SCSL_SOMI)S}
28 t_{dis(SCSH_SOMI)S}
29 t_{ena(SCSL_ENA)S}
30 t_{dis(SPC_ENA)S}
PARAMATER
Required delay from SPI0_SCS asserted at slave to first
SPI0_CLK edge at slave.
Polarity = 0, Phase = 0,
from SPI0_CLK falling
Required delay from final SPI0_CLK
edge before SPI0_SCS is
deasserted.
Polarity = 0, Phase = 1,
from SPI0_CLK falling
Polarity = 1, Phase = 0,
from SPI0_CLK rising
Polarity = 1, Phase = 1,
from SPI0_CLK rising
Delay from master asserting SPI0_SCS to slave driving
SPI0_SOMI valid
Delay from master deasserting SPI0_SCS to slave 3-stating
SPI0_SOMI
Delay from master deasserting SPI0_SCS to slave driving
SPI0_ENA valid
Polarity = 0, Phase = 0,
from SPI0_CLK falling
Delay from final clock receive edge
on SPI0_CLK to slave 3-stating or
driving high SPI0_ENA.⁽⁴⁾
Polarity = 0, Phase = 1,
from SPI0_CLK rising
Polarity = 1, Phase = 0,
from SPI0_CLK rising
Polarity = 1, Phase = 1,
from SPI0_CLK falling
MIN
2P
0.5t_c(SPC)M + P +
5
P+5
0.5t_c(SPC)M + P +
5
P+5
MAX
UNIT
ns
ns
P + 18.5 ns
P + 18.5 ns
18.5 ns
2.5 P + 18.5
2.5 P + 18.5
ns
2.5 P + 18.5
2.5 P + 18.5
(1) These parameters are in addition to the general timings for SPI slave modes (Table 5-55).
(2) P = SYSCLK2 period
(3) Figure shows only Polarity = 0, Phase = 0 as an example. Table gives parameters for all four slave clocking modes.
(4) SPI0_ENA is driven low after the transmission completes if the SPIINT0.ENABLE_HIGHZ bit is programmed to 0. Otherwise it is 3-
stated. If 3-stated, an external pullup resistor should be used to provide a valid level to the master. This option is useful when tying
several SPI slave devices to a single master.
No.
1 t_c(SPC)M
2 t_w(SPCH)M
3 t_w(SPCL)M
4 t_{d(SIMO_SPC)M}
Table 5-62. General Timing Requirements for SPI1 Master Modes⁽¹⁾
PARAMATER
Cycle Time, SPI1_CLK, All Master Modes
Pulse Width High, SPI1_CLK, All Master Modes
Pulse Width Low, SPI1_CLK, All Master Modes
Polarity = 0, Phase =
0,
to SPI1_CLK rising
Delay, initial data bit valid on
SPI1_SIMO to initial edge on
SPI1_CLK ⁽²⁾
Polarity = 0, Phase =
1,
to SPI1_CLK rising
Polarity = 1, Phase =
0,
to SPI1_CLK falling
Polarity = 1, Phase =
1,
to SPI1_CLK falling
MIN
greater of 3P or 20 ns
0.5t_c(SPC)M - 1
0.5t_c(SPC)M - 1
MAX
UNIT
256P ns
ns
ns
5
- 0.5t_c(SPC)M + 5
ns
5
- 0.5t_c(SPC)M + 5
(1) P = SYSCLK2 period
(2) First bit may be MSB or LSB depending upon SPI configuration. MO(0) refers to first bit and MO(n) refers to last bit output on
SPI1_SIMO. MI(0) refers to the first bit input and MI(n) refers to the last bit input on SPI1_SOMI.
140 Peripheral Information and Electrical Specifications
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