THS3120_16 Datasheet, PDF (19/35 Pages) Texas Instruments – LOW-NOISE, HIGH-OUTPUT DRIVE, CURRENT-FEEDBACK OPERATIONAL AMPLIFIERS

THS3120
THS3121
www.ti.com........................................................................................................................................ SLOS420E – SEPTEMBER 2003 – REVISED OCTOBER 2009
Figure 58 shows the total system output impedance
which includes the amplifier output impedance in
parallel with the feedback plus gain resistors, which
cumulate to 1298 Ω. Figure 47 shows this circuit
configuration for reference.
1400
1200
1000
800
600
400
200
0
100 k
Gain = 2
R_F = 649 Ω
V_S = ±15 V and ±5 V
1M
10 M
100 M 1 G
f − Frequency − Hz
Figure 58. Power-down Output Impedance vs
Frequency
As with most current-feedback amplifiers, the internal
architecture places some limitations on the system
when in power-down mode. Most notably is the fact
that the amplifier actually turns ON if there is a ±0.7 V
or greater difference between the two input nodes
(V+ and V–) of the amplifier. If this difference
exceeds ±0.7 V, the output of the amplifier creates an
output voltage equal to approximately [(V+) – (V–) –
0.7 V] × Gain. Also, if a voltage is applied to the
output while in power-down mode, the V– node
voltage is equal to V_O(applied) × R_G/(R_F + R_G). For low
gain configurations and a large applied voltage at the
output, the amplifier may actually turn ON due to the
aforementioned behavior.
The time delays associated with turning the device on
and off are specified as the time it takes for the
amplifier to reach either 10% or 90% of the final
output voltage. The time delays are in the order of
microseconds because the amplifier moves in and out
of the linear mode of operation in these transitions.
POWER-DOWN REFERENCE PIN
OPERATION
In addition to the power-down pin, the THS3120
features a reference pin (REF) which allows the user
to control the enable or disable power-down voltage
levels applied to the PD pin. In most split-supply
applications, the reference pin is connected to
ground. In either case, the user needs to be aware of
voltage-level thresholds that apply to the power-down
pin. Table 2 shows examples and illustrate the
relationship between the reference voltage and the
power-down thresholds. In the table, the threshold
levels are derived by the following equations:
PD ≤ REF + 0.8 V for enable
PD ≥ REF + 2 V for disable
where the usable range at the REF pin is
V_S– ≤ V_REF ≤ (V_S+ – 4 V).
The recommended mode of operation is to tie the
REF pin to midrail, thus settings the enable/disable
threshold to V_(midrail) + 0.8 V and V_(midrail) = 2 V
respectively.
Table 2. Power-Down Threshold Voltage Levels
REFERENCE
SUPPLY
PIN
VOLTAGE (V) VOLTAGE (V)
±15, ±5
0
±15
2
±15
–2
±5
1
±5
–1
30
15
10
5
ENABLE
LEVEL (V)
0.8
2.8
–1.2
1.8
–0.2
15.8
5.8
DISABLE
LEVEL (V)
2
4
0
3
1
17
7
Note that if the REF pin is left unterminated, it floats
to the positive rail and falls outside of the
recommended operating range given above (V_S– ≤
V_REF ≤ V_S+ – 4 V). As a result, it no longer serves as
a reliable reference for the PD pin, and the
enable/disable thresholds given above no longer
apply. If the PD pin is also left unterminated, it floats
to the positive rail and the device is disabled. If
balanced, split supplies are used (±V_S) and the REF
and PD pins are grounded, the device is enabled.
Copyright © 2003–2009, Texas Instruments Incorporated
Product Folder Link(s): THS3120 THS3121
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