LMH0303 Datasheet, PDF (19/27 Pages) National Semiconductor (TI) – 3 Gbps HD/SD SDI Cable Driver with Cable Detect

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10 Layout
LMH0303
SNLS285H – APRIL 2008 – REVISED MAY 2016
10.1 Layout Guidelines
TI recommends the following layout guidelines for the LMH0303:
1. The R_REF 1% tolerance resistor should be placed as close as possible to the R_REF pin. In addition, the copper
in the plane layers below the R_REF network should be removed to minimize parasitic capacitance.
2. Choose a suitable board stackup that supports 75-Ω single-ended trace and 100-Ω differential trace routing
on the top layer of the board. This is typically done with a Layer 2 ground plane reference for the 100-Ω
differential traces and a second ground plane at Layer 3 reference for the 75-Ω single-ended traces.
3. Use single-ended uncoupled trace designed with 75-Ω impedance for signal routing to SDO and SDO. The
trace width is typically 8-10 mil reference to a ground plane at Layer 3.
4. Use coupled differential traces with 100-Ω impedance for signal routing to SDI and SDI. They are usually 5-
mil to 8-mil trace width reference to a ground plane at Layer 2.
5. Place anti-pad (ground relief) on the power and ground planes directly under the 4.7-μF AC-coupling
capacitor, return loss network, and IC landing pads to minimize parasitic capacitance. The size of the anti-
pad depends on the board stackup and can be determined by a 3-dimension electromagnetic simulation tool.
6. Use a well-designed BNC footprint to ensure the BNC’s signal landing pad achieves 75-Ω characteristic
impedance. BNC suppliers usually provide recommendations on BNC footprint for best results.
7. Keep trace length short between the BNC and SDO. The trace routing for SDO and SDO should be
symmetrical, approximately equal lengths, and equal loading.
8. The exposed pad EP of the package should be connected to the ground plane through an array of vias.
These vias are solder-masked to avoid solder flow into the plated-through holes during the board
manufacturing process.
9. Connect each supply pin (V_CC and V_EE) to the power or ground planes with a short via. The via is usually
placed tangent to the landing pads of the supply pins with the shortest trace possible.
10. Power-supply bypass capacitors should be placed close to the supply pins.
10.2 Layout Example
Figure 8 shows an example of proper layout requirements for the LMH0303.
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