LMH0303 Datasheet, PDF (14/27 Pages) National Semiconductor (TI) – 3 Gbps HD/SD SDI Cable Driver with Cable Detect

LMH0303
SNLS285H – APRIL 2008 – REVISED MAY 2016
www.ti.com
Register Maps (continued)
ADDRESS
0x05
R/W
NAME
R/W OUTPUTCTRL
0x06
0x07
0x08
R/W RSVD
R/W RSVD
R/W TEST
Table 1. SMBus Registers (continued)
BITS
7
6
FIELD
RSVD
FLOSOF
5 FLOSON
4 LOSEN
3 MUTE
2:0 SDTFThresh
7:0 RSVD
7:0 RSVD
7:5 CMPCMD
4:0 RSVD
DEFAULT
0
0
0
0
0
010
00000000
00000000
000
00000
DESCRIPTION
Reserved as 0. Always write 0 to this bit.
Force LOS to always OFF in regards to its
effect on the output signal. This forces the
device into either the mute or “add offset”
state. The LOS bit in register 0x01 still reflects
the correct state of LOS.
0: LOS operates normally, muting or adding
offset as specified by the MUTE bit.
1: Muting or adding offset is always in place
as specified by the MUTE bit.
Force LOS to always ON in regards to its
effect on the output signal. This prevents the
device from muting or adding offset. The LOS
bit in register 0x01 still reflects the correct
state of LOS.
0: LOS operates normally, muting or adding
offset as specified in the MUTE bit.
1: Muting or adding offset never occurs.
Configures LOS to be combined with the
ENABLE functionality.
0: Only the PD bit and ENABLE pin affect the
power down state of the output drivers.
1: If the ENABLE pin is set to ground, it
powers down the output drivers regardless of
the state of LOS or the PD bit. With the
ENABLE pin set to V_CC, LOS=0 will power
down the output drivers, and LOS=1 will leave
the power down state dependent on the PD
bit.
Selects whether the device will MUTE when
loss of signal is detected or add an offset to
prevent self oscillation. When an input signal
is detected (LOS=1), the device will operate
normally.
0: Loss of signal will force a small offset to
prevent self oscillation.
1: Loss of signal will force the channel to
MUTE.
Sets the Termination Fault threshold for SDO,
when SD is set to SD rate. Combines with
SDTFThreshLSB in register 0x03 (default for
combined value is 0101).
Reserved as 00000000. Always write
00000000 to these bits.
Reserved as 00000000. Always write
00000000 to these bits.
Compare command. Determines whether the
peak value or the current value of the
Termination Fault counters is read in registers
0x0A and 0x0B.
000: Resets compare value to 00; registers
0x0A and 0x0B show current counter values.
Sets detection to look for MAX peak values.
001: Capture counter 0. Register 0x0A shows
peak value.
010: Capture counter 1. Register 0x0B shows
peak value.
011, 100: Reserved.
101: Resets compare value to 0x1F. Sets
detection to look for MIN peak values.
110, 111: Reserved.
Reserved as 00000. Always write 00000 to
these bits.
14
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