HD3SS215_15 Datasheet, PDF (19/31 Pages) Texas Instruments – HD3SS215 6.0 Gbps HDMI DisplayPort 2:1/1:2 Differential Switch

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11 Layout
HD3SS215, HD3SS215I
SLAS971C – MAY 2014 – REVISED AUGUST 2015
11.1 Layout Guidelines
• The ESD and EMI protection devices (if used) should be placed as close as possible to the connector.
• Place voltage regulators as far away as possible from the high-speed differential pairs.
• It is recommended that small decoupling capacitors for the HD3SS215 power rail be placed close to the
device.
• The high-speed differential signal traces should be routed on the top layer to avoid the use of vias and allow
clean interconnects to the mux.
• The high speed differential signal traces should be routed parallel to each other as much as possible. It is
recommended the traces be symmetrical.
• In order to control impedance for transmission lines, a solid ground plane should be placed next to the high-
speed signal layer. This also provides an excellent low-inductance path for the return current flow.
• The power plane should be placed next to the ground plane to create additional high-frequency bypass
capacitance.
• Adding test points will cause impedance discontinuity and will therefore negatively impact signal performance.
If test points are used, they should be placed in series and symmetrically. They must not be placed in a
manner that causes stubs on the differential pair.
• Avoid 90 degree turns in traces. The use of bends in differential traces should be kept to a minimum. When
bends are used, the number of left and right bends should be as equal as possible and the angle of the bend
should be ≥135 degrees. This will minimize any length mismatch caused by the bends and therefore minimize
the impact bends have on EMI.
11.2 Layout Example
An example layout for the HD3SS215 shows the device implemented on a 4 layer board. The layout figures
follow the DisplayPort application schematic above. The top layer layout view shows the signal routing for two
sources and one sink. The bottom layer layout view shows the remaining signal routing and a copper pour
implemented for the decoupling capacitors.
Figure 8. Top Layer Layout View
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