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| ADS8372 Datasheet, PDF (19/36 Pages) Texas Instruments – 16-BIT, 600-kHz, FULLY DIFFERENTIAL PSEUDO-BIPOLAR INPUT, MICROPOWER SAMPLING ANALOG-TO-DIGITAL CONVERTER WITH SERIAL INTERFACE AND REFERENCE | |||
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ADS8372
SLAS451 â JUNE 2005
SCLK
1
2
3
4 16 17 18
19
tsu5
tcyc
th5
td14
CS
tw2
CONVST
SDO
BUSY
tquiet3
td13
MSB
D15 D14 D13 D12 D1
td12
tquiet1
LSB
D0 D0 D0 D15 Repeated
If There is 19th SCLK
Donât Care
(D0 Repeated)
tquiet2
Conversion N
tsu2
CS Fall Before This
Point Reads Data
From Conversion
Nâ1
No CS
Fall
Zone
th2
CS Fall After This
Point Reads Data
From Conversion
N
Conversion N+1
Figure 45. Read Frame Controlled via CS (FS = 1)
If another data frame is attempted (by pulling CS high and then low) during an active data frame, then the
ongoing frame is aborted and a new frame is started.
2. Serial interface using FS:
A data read operation in this mode is shown in Figure 46 and Figure 47. The MSB of the output data is
available at the rising edge of FS. MSB â 1 is shifted out at the first rising edge after the first falling edge of
SCLK after the FS falling edge. Subsequent bits are shifted at the subsequent rising edges of SCLK.
SCLK
1
2
3
4
16
17
18
19
th6
tcyc
CS
tsu7
tsu6
tw3
FS
CONVST
td15
SDO
BUSY
td13
MSB of Conversion N
D15
D14
D13 D12 D1
tquiet1
LSB
D0
D0
D0
D15 Repeated
If There is 19th SCLK
Donât Care
(D0 Repeated)
Conversion N
Figure 46. Read Frame Controlled via FS (FS is Low When BUSY Falls)
tquiet2
Conversion N+1
If FS is high when BUSY falls, the SDO is updated again with the new MSB when BUSY falls. This is shown
in Figure 47.
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