OPA4313 Datasheet, PDF (18/38 Pages) Texas Instruments – 1-MHz, Micro-Power, Low-Noise, RRIO,1.8-V CMOS OPERATIONAL AMPLIFIER

OPA313
OPA2313
OPA4313
SBOS649C – SEPTEMBER 2012 – REVISED MARCH 2013
www.ti.com
CAPACITIVE LOAD AND STABILITY
The OPA313 is designed to be used in applications where driving a capacitive load is required. As with all op
amps, there may be specific instances where the OPA313 can become unstable. The particular op amp circuit
configuration, layout, gain, and output loading are some of the factors to consider when establishing whether or
not an amplifier is stable in operation. An op amp in the unity-gain (+1-V/V) buffer configuration that drives a
capacitive load exhibits a greater tendency to be unstable than an amplifier operated at a higher noise gain. The
capacitive load, in conjunction with the op amp output resistance, creates a pole within the feedback loop that
degrades the phase margin. The degradation of the phase margin increases as the capacitive loading increases.
When operating in the unity-gain configuration, the OPA313 remains stable with a pure capacitive load up to
approximately 1 nF. The equivalent series resistance (ESR) of some very large capacitors (C_L greater than 1 μF)
is sufficient to alter the phase characteristics in the feedback loop such that the amplifier remains stable.
Increasing the amplifier closed-loop gain allows the amplifier to drive increasingly larger capacitance. This
increased capability is evident when observing the overshoot response of the amplifier at higher voltage gains.
See the typical characteristic graph, Small-Signal Overshoot vs. Capacitive Load.
One technique for increasing the capacitive load drive capability of the amplifier operating in a unity-gain
configuration is to insert a small resistor, typically 10 Ω to 20 Ω, in series with the output, as shown in Figure 36.
This resistor significantly reduces the overshoot and ringing associated with large capacitive loads. One possible
problem with this technique, however, is that a voltage divider is created with the added series resistor and any
resistor connected in parallel with the capacitive load. The voltage divider introduces a gain error at the output
that reduces the output swing.
V+
R_S
Device
V_OUT
V_IN
10 W to
20 W
R_L
C_L
Figure 36. Improving Capacitive Load Drive
DFN PACKAGE
The OPA2313 (dual version) uses the DFN style package (also known as SON); this package is a QFN with
contacts on only two sides of the package bottom. This leadless package maximizes printed circuit board (PCB)
space and offers enhanced thermal and electrical characteristics through an exposed pad. One of the primary
advantages of the DFN package is its low, 0.9-mm height. DFN packages are physically small, have a smaller
routing area, improved thermal performance, reduced electrical parasitics, and use a pinout scheme that is
consistent with other commonly-used packages, such as SO and MSOP. Additionally, the absence of external
leads eliminates bent-lead issues.
The DFN package can easily be mounted using standard PCB assembly techniques. See Application Note,
QFN/SON PCB Attachment (SLUA271) and Application Report, Quad Flatpack No-Lead Logic Packages
(SCBA017), both available for download from www.ti.com.
NOTE
The exposed leadframe die pad on the bottom of the DFN package should be connected
to the most negative potential (V–).
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