OPA377-Q1_16 Datasheet, PDF (18/31 Pages) Texas Instruments – Low-Noise, Low Quiescent Current, Precision Automotive Grade Operational Precision Automotive Grade Operational

OPA377-Q1, OPA2377-Q1, OPA4377-Q1
SBOS797A – MAY 2016 – REVISED MAY 2016
www.ti.com
9 Power Supply Recommendations
The OPAx377-Q1 family of devices is specified for operation from 2.2 V to 5.5 V (±1.1 V to ±2.75 V); many
specifications apply from –40°C to +125°C. Parameters that can exhibit significant variance with regard to
operating voltage or temperature are presented in the Typical Characteristics section.
10 Layout
10.1 Layout Guidelines
For best operational performance of the device, use good printed circuit board (PCB) layout practices,
including:
• Noise can propagate into analog circuitry through the power pins of the circuit as a whole and op amp
itself. Bypass capacitors are used to reduce the coupled noise by providing low-impedance power
sources local to the analog circuitry.
– Connect low-ESR, 0.1-µF ceramic bypass capacitors between each supply pin and ground,
placed as close to the device as possible. A single bypass capacitor from V+ to ground is
applicable for single-supply applications.
• Separate grounding for analog and digital portions of circuitry is one of the simplest and most-
effective methods of noise suppression. One or more layers on multilayer PCBs are usually devoted
to ground planes. A ground plane helps distribute heat and reduces EMI noise pickup. Make sure to
physically separate digital and analog grounds paying attention to the flow of the ground current. For
more detailed information refer to the application report, Circuit Board Layout Techniques, SLOA089.
• In order to reduce parasitic coupling, run the input traces as far away from the supply or output traces
as possible. If these traces cannot be kept separate, crossing the sensitive trace perpendicular is
much better as opposed to in parallel with the noisy trace.
• Place the external components as close to the device as possible. As shown in Figure 28, keeping
RF and RG close to the inverting input minimizes parasitic capacitance.
• Keep the length of input traces as short as possible. Always remember that the input traces are the
most sensitive part of the circuit.
• Consider a driven, low-impedance guard ring around the critical traces. A guard ring can significantly
reduce leakage currents from nearby traces that are at different potentials.
• Cleaning the PCB following board assembly is recommended for best performance.
• Any precision integrated circuit may experience performance shifts due to moisture ingress into the
plastic package. Following any aqueous PCB cleaning process, baking the PCB assembly is
recommended to remove moisture introduced into the device packaging during the cleaning process.
A low temperature, post cleaning bake at 85°C for 30 minutes is sufficient for most circumstances.
10.2 Layout Example
VIN
RG
+
±
RF
VOUT
Copyright © 2016,
Texas Instruments Incorporated
Figure 27. Typical Schematic for PCB Layout Example
18
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Product Folder Links: OPA377-Q1 OPA2377-Q1 OPA4377-Q1