LP2992_15 Datasheet, PDF (18/35 Pages) Texas Instruments – LP2992 Micropower 250-mA Low-Noise Ultralow-Dropout Regulator in SOT-23 and WSON Packages Designed for Use with Very Low-ESR Output Capacitors

LP2992
SNVS171I – NOVEMBER 2001 – REVISED NOVEMBER 2015
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8.2.2.2.1 Tantalum
Tantalum capacitors are less desirable than ceramics for use as output capacitors because they are more
expensive when comparing equivalent capacitance and voltage ratings in the 1-µF to 4.7-µF range.
Another important consideration is that tantalum capacitors have higher ESR values than equivalent size
ceramics. This means that while it may be possible to find a Tantalum capacitor with an ESR value within the
stable range, it would have to be larger in capacitance (which means bigger and more costly) than a ceramic
capacitor with the same ESR value.
It should also be noted that the ESR of a typical tantalum increases about 2:1 as the temperature goes from
25°C down to −40°C, so some guard band must be allowed.
8.2.2.3 Reverse Input-Output Voltage
The PNP power transistor used as the pass element in the LP2992 has an inherent diode connected between
the regulator output and input. During normal operation (where the input voltage is higher than the output) this
diode is reverse-biased.
However, if the output is pulled above the input, this diode turns ON and current flows into the regulator output.
In such cases, a parasitic SCR can latch which allows a high current to flow into V_IN (and out the ground pin),
which can damage the part.
In any application where the output may be pulled above the input, an external Schottky diode must be
connected from V_IN to V_OUT (cathode on V_IN, anode on V_OUT), to limit the reverse voltage across the LP2992 to
0.3 V (see Absolute Maximum Ratings).
8.2.2.4 Power Dissipation
Knowing the device power dissipation and proper sizing of the thermal plane connected to the tab or pad is
critical to ensuring reliable operation. Device power dissipation depends on input voltage, output voltage, and
load conditions and can be calculated with Equation 1.
P_D(MAX) = (V_IN(MAX) – V_OUT) × I_OUT
(1)
Power dissipation can be minimized, and greater efficiency can be achieved, by using the lowest available
voltage drop option that would still be greater than the dropout voltage (V_DO). However, keep in mind that higher
voltage drops result in better dynamic (that is, PSRR and transient) performance.
On the WSON (NGD) package, the primary conduction path for heat is through the exposed power pad to the
PCB. To ensure the device does not overheat, connect the exposed pad, through thermal vias, to an internal
ground plane with an appropriate amount of copper PCB area.
On the SOT-23 (DBV) package, the primary conduction path for heat is through the pins to the PCB. The
maximum allowable junction temperature (T_J(MAX))determines maximum power dissipation allowed (P_D(MAX)) for
the device package.
Power dissipation and junction temperature are most often related by the junction-to-ambient thermal resistance
(R_θJA) of the combined PCB and device package and the temperature of the ambient air (T_A), according to
Equation 2 or Equation 2:
T_J(MAX) = T_A(MAX) + ( R_θJA × P_D(MAX))
(2)
P_D = T_J(MAX) – T_A(MAX) / R_θJA
(3)
Unfortunately, this R_θJA is highly dependent on the heat-spreading capability of the particular PCB design, and
therefore varies according to the total copper area, copper weight, and location of the planes. The R_θJA recorded
in Thermal Information is determined by the specific EIA/JEDEC JESD51-7 standard for PCB and copper-
spreading area, and is to be used only as a relative measure of package thermal performance. For a well-
designed thermal layout, R_θJA is actually the sum of the package junction-to-case (bottom) thermal resistance
(R_θJCbot) plus the thermal resistance contribution by the PCB copper area acting as a heat sink.
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