DS92LV3241_15 Datasheet, PDF (18/31 Pages) Texas Instruments – 20-85 MHz 32-Bit Channel Link II Serializer / Deserializer

DS92LV3241, DS92LV3242
SNLS314D – SEPTEMBER 2009 – REVISED APRIL 2013
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To enable the Pre-Emphasis function, the “PRE” pin requires one external resistor (Rpre) to VSS (GND) in order
to set the pre-emphasized current level. Options include:
1. Normal Output (no Pre-emphasis) – Leave the PRE pin open, include an R pad, do not populate.
2. Enhanced Output (Pre-emphasis enabled) – connect a resistor on the PRE pin to Vss.
Values of the Rpre Resistor should be between 12K Ohm and 100K Ohm. Values less than 6K Ohm should not
be used. The amount of Pre-Emphasis for a given media will depend on the transmission distance and Fmax of
the application. In general, too much Pre-Emphasis can cause over or undershoot at the receiver input pins. This
can result in excessive noise, crosstalk, reduced Fmax, and increased power dissipation. For shorter cables or
distances, Pre-Emphasis is typically not be required. Signal quality measurements should be made at the end of
the application cable to confirm the proper amount of Pre-Emphasis for the specific application.
The Pre-Emphasis circuit increases the drive current to I = 48 / (R_PRE). For example if R_PRE = 15 kOhms, then
the current is increased by an additional 3.2 mA. To calculate the expected increase in V_OD, multiply the increase
in current by 50 ohms. So for the case of R_PRE = 15 kOhms, the boost to V_OD would be 3.2 mA x 50 Ohms = 160
mV. The duration of the current is controlled to one bit by time. If more than one bit value is repeated in the next
cycle(s), the Pre-Emphasis current is turned off (back to the normal output current level) for the next bit(s). To
boost high frequency data and pre-equalize teh data patternreduce ISI (Inter-Symbol Interference) improving the
resulting eye pattern.
V_OD SELECT
The SER Line Driver Differential Output Voltage (V_OD) magnitude is selectable. Two levels are provided and are
selected by the VSEL pin. When this pin is LOW, normal output levels are obtained. For most application set the
VSEL pin LOW. When this pin is HIGH, the output current is increased to double the V_OD level. Use this setting
only for extra long cables or high-loss interconnects.
VSEL Pin Setting
LOW
HIGH
Table 1. VOD Control
Effect
Small V_OD, typ 440 mV_P-P
Large V_OD, typ 850 mV_P-P
SERIAL INTERFACE
The serial links between the DS92LV3241 and the DS92LV3242 are intended for a balanced 100 Ohm
interconnects. The links must be configured as an AC coupled interface.
The SER and DES support AC-coupled interconnects through an integrated DC balanced encoding/decoding
scheme. An external AC coupling capacitors must be placed, in series, in the LVDS signal path. The DES input
stage is designed for AC-coupling by providing a built-in AC bias network which sets the internal common mode
voltage (VCM) to +1.8V.
For the high-speed LVDS transmission, small footprint packages should be used for the AC coupling capacitors.
This will help minimize degradation of signal quality due to package parasitics. NPO class 1 or X7R class 2 type
capacitors are recommended. 50 WVDC should be the minimum used for best system-level ESD performance.
The most common used capacitor value for the interface is 100 nF (0.1 uF) capacitor. One set of capacitors may
be used for isolation. Two sets (both ends) may also be used for maximum isolation of both the SER and DES
from cable faults.
The DS92LV3241 and the DS92LV3242 differential I/O’s are internally terminated with 100 Ohm resistance
between the inverting and non-inverting pins and do not require external termination. The internal resistance
value will be between 90 ohm and 130 ohm. The integrated terminations improve signal integrity, reduce stub
lengths, and decrease the external component count resulting in space savings.
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