DS92LV3241_15 Datasheet, PDF (16/31 Pages) Texas Instruments – 20-85 MHz 32-Bit Channel Link II Serializer / Deserializer

DS92LV3241, DS92LV3242
SNLS314D – SEPTEMBER 2009 – REVISED APRIL 2013
www.ti.com
FUNCTIONAL DESCRIPTION
The DS92LV3241 Serializer (SER) and DS92LV3242 Deserializer (DES) chipset is a flexible SER/DES chipset
that translates a 32-bit parallel LVCMOS data bus into a quad (4 pairs) or dual (2 pairs) LVDS serial links with
embedded clock. The DS92LV3241 serializes the 32-bit wide parallel LVCMOS word into four or two high-speed
LVDS serial data streams with embedded clock, scrambles and DC Balances the data to support AC coupling
and enhance signal quality. The DS92LV3242 receives the dual/quad LVDS serial data streams and converts it
back into a 32-bit wide parallel data with a recovered clock. The dual/quad LVDS serial data stream reduces
cable size, the number of connectors, and eases skew concerns.
Parallel clocks between 20 MHz to 85 MHz are supported by the dual or quad operating modes. The modes are
user selectable through a control pin on Serializer. In dual mode, the transmit clock frequency supports 20 MHz
to 50 MHz and in quad mode the transmit clock frequency supports 40 MHz to 85 MHz. In the dual mode
configuration, the embedded clock LVDS serial streams have an effective data payload of 640 Mbps (20MHz x
32-bit) to 1.6 Gbps (50MHz x 32- bit). In the quad mode configuration, the embedded clock LVDS serial streams
have an effective data payload of 1.28 Gbps (40MHz x 32-bit) to 2.72 Gbps (85MHz x 32-bit). The SER/DES
chipset is designed to transmit data over long distances through standard twisted pair (TWP) cables. The
differential inputs and outputs are internally terminated with 100 ohm resistors to provide source and load
termination, minimize stub length, to reduce component count and further minimize board space.
The DES can attain lock to a data stream without the use of a separate reference clock source; greatly
simplifying system complexity and reducing overall cost. The DES synchronizes to the SER regardless of data
pattern, delivering true automatic “plug-and-lock” performance. It will lock to the incoming serial stream without
the need of special training patterns or special sync characters. The DES recovers the clock and data by
extracting the embedded clock information, deskews the serial data channels and then deserializes the data. The
DES also monitors the incoming clock information, determines lock status, and asserts the LOCK output high
when lock occurs. In addition the DES also supports an optional AT-SPEED BIST (Built In Self Test) mode, BIST
error flag, and LOCK status reporting pin. The SER and the DES have a power down control signal to enable
efficient operation in various applications.
DESKEW AND CHANNEL ALIGNMENT
The DES automatically detects dual or quad serial channel mode and provides a clock alignment and deskew
function without the need for any special training patterns. During the locking phase, the embedded clock
information is recovered on all channels and the serial links are internally synchronized, de-skewed, and auto
aligned. The internal CDR circuitry will dynamically compensate for up to 0.4 times the parallel clock period of
per channel phase skew (channel-to-channel) between the recovered clocks of the serial links. This provides
skew phase tolerance from mismatches in interconnect wires such as PCB trace routing, cable pair-to-pair length
differences, and connector imbalances.
DATA TRANSFER
After SER lock is established (SER PLL to TxCLKIN), the inputs TxIN0–TxIN31 are latched into the encoder
block. Data is clocked into the SER by the TxCLKIN input. The edge of TxCLKIN used to strobe the data is
selectable via the R_FB (SER) pin. R_FB (SER) high selects the rising edge for clocking data and low selects
the falling edge. The SER outputs (TxOUT[3:0]+/-) are intended to drive a AC Coupled point-to-point
connections.
The SER latches 32-bit parallel data bus and performs several operations to it. The 32-bit parallel data is
internally encoded and sequentially transmitted over the two high-speed serial LVDS channels. For each serial
channel, the SER transmits 20 bits of information per payload to the DES. In the dual mode, the 32-bit parallel
data is scaled and bit-mapped across two 20-bit data payloads per channel, resulting in a per channel throughput
of 400 Mbps to 1.0 Gbps (20 bits x clock rate). Under quad mode, the internal PLL operates at ½ the input clock
frequency rate. The 32 bits are bit-mapped and sequenced per every 2 cycles at ½ the TxCLKIN frequency
across four channels, resutling in a per channel throughput of 400 Mbps to 850 Mbps (20 bits x clock rate/2). The
chipset supports frequency ranges of 20 MHz to 85 MHz.
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