TMS320F28379D Datasheet, PDF(179/212 Page) Texas Instruments

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TMS320F28379D Datasheet, PDF (179/212 Pages) Texas Instruments – Dual-Core Delfino Microcontrollers

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TMS320F28379D, TMS320F28377D

TMS320F28376D, TMS320F28375D, TMS320F28374D

SPRS880F â DECEMBER 2013 â REVISED NOVEMBER 2015

6.3.3 EMIF Chip Select Memory Map

The EMIF1 memory map is the same for both CPU subsystems. EMIF2 is available only on the CPU1

subsystem. The EMIF memory map is shown in Table 6-4.

Table 6-4. EMIF Chip Select Memory Map

EMIF CHIP SELECT

SIZE

EMIF1_CS0n - Data

256M x 16

EMIF1_CS2n - Program + Data

2M x 16

EMIF1_CS3n - Program + Data

512K x 16

EMIF1_CS4n - Program + Data

EMIF2_CS0n - Data(1)

EMIF2_CS2n - Program + Data(1)

393K x 16

64M x 16

4K x 16

(1) Available only on the CPU1 subsystem.

START ADDRESS

0x8000 0000

0x0010 0000

0x0030 0000

0x0038 0000

0x9000 0000

0x0000 2000

END ADDRESS

0x8FFF FFFF

0x002F FFFF

0x0037 FFFF

0x003D FFFF

0x93FF FFFF

0x0000 2FFF

CLA ACCESS

DMA ACCESS

Yes

Yes (Data only)

6.3.4 Peripheral Registers Memory Map

The peripheral registers memory map can be found in Table 6-5. The peripheral registers can be assigned

to either the CPU1 or CPU2 subsystems except where noted in Table 6-5. Registers in the peripheral

frames share a secondary master (CLA or DMA) selection with all other registers within the same

peripheral frame. See the TMS320F2837xD Dual-Core Delfino Microcontrollers Technical Reference

Manual (SPRUHM8) for details on the CPU subsystem and secondary master selection.

Table 6-5. Peripheral Registers Memory Map

REGISTERS

AdcaResultRegs

AdcbResultRegs

AdccResultRegs

AdcdResultRegs

CpuTimer0Regs(1)

CpuTimer1Regs(1)

CpuTimer2Regs(1)

PieCtrlRegs(1)

Cla1SoftIntRegs

DmaRegs(1)

Cla1Regs(1)

EPwm1Regs

EPwm2Regs

EPwm3Regs

EPwm4Regs

EPwm5Regs

EPwm6Regs

EPwm7Regs

EPwm8Regs

EPwm9Regs

EPwm10Regs

EPwm11Regs

EPwm12Regs

STRUCTURE NAME

ADC_RESULT_REGS

CPUTIMER_REGS

PIE_CTRL_REGS

START

ADDRESS

0x0000 0B00

0x0000 0B20

0x0000 0B40

0x0000 0B60

0x0000 0C00

0x0000 0C08

0x0000 0C10

0x0000 0CE0

CLA_SOFTINT_REGS

0x0000 0CE0

DMA_REGS

0x0000 1000

CLA_REGS

0x0000 1400

Peripheral Frame 1

EPWM_REGS

0x0000 4000

EPWM_REGS

0x0000 4100

EPWM_REGS

0x0000 4200

EPWM_REGS

0x0000 4300

EPWM_REGS

0x0000 4400

EPWM_REGS

0x0000 4500

EPWM_REGS

0x0000 4600

EPWM_REGS

0x0000 4700

EPWM_REGS

0x0000 4800

EPWM_REGS

0x0000 4900

EPWM_REGS

0x0000 4A00

EPWM_REGS

0x0000 4B00

END ADDRESS

CLA

ACCESS

0x0000 0B1F

Yes

0x0000 0B3F

Yes

0x0000 0B5F

Yes

0x0000 0B7F

Yes

0x0000 0C07

0x0000 0C0F

0x0000 0C17

0x0000 0CFF

Yes â CLA

only, no

CPU

access

0x0000 11FF

0x0000 147F

DMA

ACCESS

Yes

0x0000 40FF

Yes

0x0000 41FF

Yes

0x0000 42FF

Yes

0x0000 43FF

Yes

0x0000 44FF

Yes

0x0000 45FF

Yes

0x0000 46FF

Yes

0x0000 47FF

Yes

0x0000 48FF

Yes

0x0000 49FF

Yes

0x0000 4AFF

Yes

0x0000 4BFF

Yes

Detailed Description 179

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