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TMS320F28379D Datasheet, PDF (1/212 Pages) Texas Instruments – Dual-Core Delfino Microcontrollers | |||
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TMS320F28379D, TMS320F28377D
TMS320F28376D, TMS320F28375D, TMS320F28374D
SPRS880F â DECEMBER 2013 â REVISED NOVEMBER 2015
TMS320F2837xD Dual-Core Delfino⢠Microcontrollers
1 Device Overview
1.1 Features
1
⢠Dual-Core Architecture
â Two TMS320C28x 32-Bit CPUs
â 200 MHz
â IEEE 754 Single-Precision Floating-Point Unit
(FPU)
â Trigonometric Math Unit (TMU)
â Viterbi/Complex Math Unit (VCU-II)
⢠Two Programmable Control Law Accelerators
(CLAs)
â 200 MHz
â IEEE 754 Single-Precision Floating-Point
Instructions
â Executes Code Independently of Main CPU
⢠On-Chip Memory
â 512KB (256KW) or 1MB (512KW) of Flash
(ECC-Protected)
â 172KB (86KW) or 204KB (102KW) of RAM
(ECC-Protected or Parity-Protected)
â Dual-Zone Security Supporting Third-Party
Development
⢠Clock and System Control
â Two Internal Zero-Pin 10-MHz Oscillators
â On-Chip Crystal Oscillator
â Windowed Watchdog Timer Module
â Missing Clock Detection Circuitry
⢠1.2-V Core, 3.3-V I/O Design
⢠System Peripherals
â Two External Memory Interfaces (EMIFs) With
ASRAM and SDRAM Support
â Dual 6-Channel Direct Memory Access (DMA)
Controllers
â Up to 169 Individually Programmable,
Multiplexed General-Purpose Input/Output
(GPIO) Pins With Input Filtering
â Expanded Peripheral Interrupt Controller (ePIE)
â Multiple Low-Power Mode (LPM) Support With
External Wakeup
⢠Communications Peripherals
â USB 2.0 (MAC + PHY)
â Support for 12-Pin 3.3 V-Compatible Universal
Parallel Port (uPP) Interface
â Two Controller Area Network (CAN) Modules
(Pin-Bootable)
â Three High-Speed (up to 50-MHz) SPI Ports
(Pin-Bootable)
â Two Multichannel Buffered Serial Ports
(McBSPs)
â Four Serial Communications Interfaces
(SCI/UART) (Pin-Bootable)
â Two I2C Interfaces (Pin-Bootable)
⢠Analog Subsystem
â Up to Four Analog-to-Digital Converters (ADCs)
⢠16-Bit Mode
â 1.1 MSPS Each (up to 4.4-MSPS System
Throughput)
â Differential Inputs
â Up to 12 External Channels
⢠12-Bit Mode
â 3.5 MSPS Each (up to 14-MSPS System
Throughput)
â Single-Ended Inputs
â Up to 24 External Channels
⢠Single Sample-and-Hold (S/H) on Each ADC
⢠Hardware-Integrated Post-Processing of
ADC Conversions
â Saturating Offset Calibration
â Error From Setpoint Calculation
â High, Low, and Zero-Crossing Compare,
With Interrupt Capability
â Trigger-to-Sample Delay Capture
â Eight Windowed Comparators With 12-Bit
Digital-to-Analog Converter (DAC) References
â Three 12-Bit Buffered DAC Outputs
⢠Enhanced Control Peripherals
â 24 Pulse Width Modulator (PWM) Channels
With Enhanced Features
â 16 High-Resolution Pulse Width Modulator
(HRPWM) Channels
⢠High Resolution on Both A and B Channels
of 8 PWM Modules
⢠Dead-Band Support (on Both Standard and
High Resolution)
â Six Enhanced Capture (eCAP) Modules
â Three Enhanced Quadrature Encoder Pulse
(eQEP) Modules
â Eight Sigma-Delta Filter Module (SDFM) Input
Channels, 2 Parallel Filters per Channel
⢠Standard SDFM Data Filtering
⢠Comparator Filter for Fast Action for Out of
Range
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An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
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