TM4C1292NCZAD Datasheet, PDF (177/1844 Pages) Texas Instruments – Tiva Microcontroller

Tiva^™ TM4C1292NCZAD Microcontroller
Register 61: System Handler Priority 1 (SYSPRI1), offset 0xD18
Note: This register can only be accessed from privileged mode.
The SYSPRI1 register configures the priority level, 0 to 7 of the usage fault, bus fault, and memory
management fault exception handlers. This register is byte-accessible.
System Handler Priority 1 (SYSPRI1)
Base 0xE000.E000
Offset 0xD18
Type RW, reset 0x0000.0000
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
reserved
USAGE
reserved
Type RO
RO
RO
RO
RO
RO
RO
RO
RW
RW
RW
RO
RO
RO
RO
RO
Reset
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
BUS
reserved
MEM
reserved
Type RW
RW
RW
RO
RO
RO
RO
RO
RW
RW
RW
RO
RO
RO
RO
RO
Reset
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Bit/Field
31:24
23:21
20:16
15:13
12:8
7:5
4:0
Name
reserved
USAGE
reserved
BUS
reserved
MEM
reserved
Type
RO
RW
RO
RW
RO
RW
RO
Reset
0x00
0x0
0x0
0x0
0x0
0x0
0x0
Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
Usage Fault Priority
This field configures the priority level of the usage fault. Configurable
priority values are in the range 0-7, with lower values having higher
priority.
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
Bus Fault Priority
This field configures the priority level of the bus fault. Configurable priority
values are in the range 0-7, with lower values having higher priority.
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
Memory Management Fault Priority
This field configures the priority level of the memory management fault.
Configurable priority values are in the range 0-7, with lower values
having higher priority.
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
June 18, 2014
177
Texas Instruments-Production Data