66AK2G02 Datasheet, PDF (175/240 Pages) Texas Instruments – Multicore DSP+ARM KeyStone II System-on-Chip

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1
SDx_CLK
66AK2G02
SPRS932B – DECEMBER 2015 – REVISED APRIL 2016
SDx_D
2
3
SPRS91x_TIMING_PRU_08
Figure 5-75. PRU-ICSS PRU SD_CLK Rising Active Edge
Table 5-96. PRU-ICSS PRU Timing Requirements - EnDAT Mode
NO. PARAMETER
DESCRIPTION
MIN
1
t_{w(ENDATx_IN)}
Pulse width, ENDATx_IN
40
MAX UNIT
ns
Table 5-97. PRU-ICSS PRU Switching Requirements - EnDAT Mode
NO.
2
3
4
PARAMETER
t_{w(ENDATx_CLK)}
t_{d(ENDATx_OUT-}
ENDATx_CLK)
t_{d(ENDATx_OUT_EN-}
ENDATx_CLK)
DESCRIPTION
Pulse width, ENDATx_CLK
Delay time, ENDATx_CLK fall to ENDATx_OUT
Delay time, ENDATx_CLK Fall to ENDATx_OUT_EN
MIN
20
-10
-10
MAX
10
UNIT
ns
ns
10 ns
ENDATx_IN
ENDATx_CLK
1
2
ENDATx_OUT
3
ENDATx_OUT_EN
4
Figure 5-76. PRU-ICSS PRU EnDAT Timing
SPRS91x_TIMING_PRU_09
For more information, see section Programmable Real-Time Unit Subsystem and Industrial
Communication Subsystem (PRU-ICSS) in chapter Processors and Accelerators of the device TRM.
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