66AK2G02 Datasheet, PDF (11/240 Pages) Texas Instruments – Multicore DSP+ARM KeyStone II System-on-Chip

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BALL NUMBER [1]
BALL NAME [2]
C17
AUDOSC_IN
A17
AUDOSC_OUT
N6
AVDDA_ARMPLL
W20
AVDDA_DDRPLL
N20
AVDDA_DSSPLL
G8
AVDDA_ICSSPLL
M19
AVDDA_MAINPLL
G14
AVDDA_NSSPLL
G10
AVDDA_UARTPLL
Y3
BOOTCOMPLETE
L21
CPTS_REFCLK_N
K21
CPTS_REFCLK_P
J10, J14, J16, K11, CVDD
K13, K15, K17, K9,
L10, L12, L14, L16,
L18, M11, M13,
M15, M17, M9, N10,
N12, N14, N16,
P11, P13, P15, P17,
P9, R10, R12, R14,
R16, R18, R8, T11,
T15, T17, T9, U16
J12, M5, N18, N8, CVDD1
T13
R5
DCAN0_RX
P5
DCAN0_TX
AC13
Y11
AD12
AE12
AE13
Y18
Y9
DDR3_CASn
DDR3_CBDQM
DDR3_CBDQS_N
DDR3_CBDQS_P
DDR3_RASn
DDR3_RESETn
DDR3_VREFSSTL
Y13
DDR3_WEn
SIGNAL NAME [3]
AUDOSC_IN
AUDOSC_OUT
AVDDA_ARMPLL
AVDDA_DDRPLL
AVDDA_DSSPLL
AVDDA_ICSSPLL
AVDDA_MAINPLL
AVDDA_NSSPLL
AVDDA_UARTPLL
BOOTCOMPLETE
CPTS_REFCLK_N
CPTS_REFCLK_P
CVDD
CVDD1
DCAN0_RX
GPIO1_57
DCAN0_TX
GPIO1_56
DDR3_CASn
DDR3_CBDQM
DDR3_CBDQS_N
DDR3_CBDQS_P
DDR3_RASn
DDR3_RESETn
DDR3_VREFSSTL
DDR3_WEn
Copyright © 2015–2016, Texas Instruments Incorporated
66AK2G02
SPRS932B – DECEMBER 2015 – REVISED APRIL 2016
Table 4-1. Pin Attributes
MUXMODE
[4]
TYPE [5]
BALL
RESET
STATE [6]
BALL
RESET
REL.
STATE [7]
BALL
RESET
REL.
MUXMODE
[8]
I/O
VOLTAGE
VALUE [9]
POWER [10]
0
I
0
1.8 V
DVDD18
0
O
0
1.8 V
DVDD18
PWR
PWR
PWR
PWR
PWR
PWR
PWR
0
OZ
PD
PD
0
3.3 V
DVDD33
0
I
0
1.8 V
DVDD18
0
I
0
1.8 V
DVDD18
PWR
HYS [11]
BUFFER
TYPE [12]
PULL
UP/DOWN
TYPE [13]
Analog
Analog
Yes
LVCMOS PU/PD
LVDS
LVDS
DSIS [14]
PWR
0
I
PU
PU
3
3
IOZ
0
OZ
PU
PU
3
3
IOZ
0
OZ
OFF
DRIVE 1 0
(OFF)
0
IOZ
OFF
OFF
0
0
IOZ
OFF
OFF
0
0
IOZ
OFF
OFF
0
0
OZ
OFF
DRIVE 1 0
(OFF)
0
OZ
OFF
DRIVE 0 0
(OFF)
0
A
0
0
OZ
OFF
DRIVE 1 0
(OFF)
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3.3 V
DVDD33
Yes
3.3 V
DVDD33
Yes
1.5 V
1.5 V
1.5 V
1.5 V
1.5 V
1.5 V
0.75 V
DVDD_DDR
DVDD_DDR
DVDD_DDR
DVDD_DDR
DVDD_DDR
DVDD_DDR
n/a
1.5 V
DVDD_DDR
LVCMOS PU/PD
0
0
LVCMOS PU/PD
0
0
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
POWER
PAD
SSTL
Terminal Configuration and Functions
11